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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15514 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2022-03-15 13:01:09 +00:00
parent 80cf2c38d4
commit 2c48a71c0b
3 changed files with 55 additions and 16 deletions
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52
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
View File

@ -69,6 +69,28 @@ NOINLINE static void adc_lld_vreg_on(ADC_TypeDef *adc) {
#endif
}
/**
* @brief Starts the ADC enable procedure.
*
* @param[in] adc pointer to the ADC registers block
*/
static void adc_lld_start_enable_adc(ADC_TypeDef *adc) {
adc->CR = ADC_CR_ADEN;
}
/**
* @brief Waits for the ADC enable procedure completion.
*
* @param[in] adc pointer to the ADC registers block
*/
static void adc_lld_wait_enable_adc(ADC_TypeDef *adc) {
while ((adc->ISR & ADC_ISR_ADRDY) == 0U) {
/* Waiting for ADC to be stable.*/
}
}
/**
* @brief Stops an ongoing conversion, if any.
*
@ -82,6 +104,12 @@ static void adc_lld_stop_adc(ADC_TypeDef *adc) {
;
adc->IER = 0;
}
/* Disabling the ADC.*/
adc->CR |= ADC_CR_ADDIS;
while ((adc->CR & ADC_CR_ADDIS) != 0U) {
/* Waiting for ADC to be disabled.*/
}
}
/**
@ -214,14 +242,8 @@ void adc_lld_start(ADCDriver *adcp) {
}
#endif /* STM32_ADC_USE_ADC1 */
/* Regulator enabled and stabilized before calibration.*/
/* Regulator enabled and stabilized.*/
adc_lld_vreg_on(ADC1);
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR = ADC_CR_ADEN;
while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
;
}
}
@ -243,15 +265,7 @@ void adc_lld_stop(ADCDriver *adcp) {
/* Restoring CCR default.*/
ADC1_COMMON->CCR = STM32_ADC_PRESC << 18;
/* Disabling ADC.*/
if (adcp->adc->CR & ADC_CR_ADEN) {
adc_lld_stop_adc(adcp->adc);
adcp->adc->CR |= ADC_CR_ADDIS;
while (adcp->adc->CR & ADC_CR_ADDIS)
;
}
/* Regulator and anything else off.*/
/* Regulator off.*/
adcp->adc->CR = 0;
#if STM32_ADC_USE_ADC1
@ -272,6 +286,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode, cfgr1, cfgr2;
const ADCConversionGroup *grpp = adcp->grpp;
/* Starting the ADC enable procedure.*/
adc_lld_start_enable_adc(adcp->adc);
/* DMA setup.*/
mode = adcp->dmamode;
cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;
@ -307,6 +324,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->SMPR = grpp->smpr;
adcp->adc->CHSELR = grpp->chselr;
/* Ensuring that the ADC finished the enable procedure.*/
adc_lld_wait_enable_adc(adcp->adc);
/* ADC configuration and start.*/
adcp->adc->CFGR1 = cfgr1;
adcp->adc->CFGR2 = cfgr2 | grpp->cfgr2;

7
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -1634,6 +1634,13 @@
*/
#define STM32_TIMCLK2 hal_lld_get_clock_point(CLK_PCLKTIM)
#if STM32_HAS_TIM1617_ERRATA
/* TIM16 and TIM17 require special handling and checks on some devices, see
the errata: "TIM16 and TIM17 are unduly clocked by SYSCLK".*/
#define STM32_TIM16CLK hal_lld_get_clock_point(CLK_SYSCLK)
#define STM32_TIM17CLK hal_lld_get_clock_point(CLK_SYSCLK)
#endif
/**
* @brief FDCAN clock point.
*/

12
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -106,6 +106,9 @@
#if defined(STM32G070xx) || defined(__DOXYGEN__)
/* Errata attributes.*/
#define STM32_HAS_TIM1617_ERRATA TRUE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
@ -292,6 +295,9 @@
#if defined(STM32G031xx) || defined(STM32G041xx)
/* Errata attributes.*/
#define STM32_HAS_TIM1617_ERRATA TRUE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
@ -472,6 +478,9 @@
#if defined(STM32G071xx) || defined(STM32G081xx)
/* Errata attributes.*/
#define STM32_HAS_TIM1617_ERRATA TRUE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
@ -662,6 +671,9 @@
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
/* Errata attributes.*/
#define STM32_HAS_TIM1617_ERRATA FALSE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE