andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[FSMC SRAM] Fixed speed degradation in testhal application. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7198 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2014-08-26 08:57:49 +00:00
parent 6220df1090
commit 2ccbae7dc4
2 changed files with 67 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

124
os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
View File

@ -584,22 +584,22 @@
#else
#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
#endif
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_MEM_D2) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D3) | \
PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_OE) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_WE) | \
#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \
PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \
NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \
PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D13) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D14) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D15) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_A16) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_A17) | \
PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D0) | \
PIN_PUPDR_PULLUP(GPIOD_MEM_D1))
PIN_PUPDR_FLOATING(GPIOD_NAND_CE1) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_A16) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_A17) | \
PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D0) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D1))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_MEM_D2) | \
PIN_ODR_HIGH(GPIOD_MEM_D3) | \
PIN_ODR_HIGH(GPIOD_PIN2) | \
@ -684,22 +684,22 @@
PIN_OSPEED_100M(GPIOE_MEM_D10) | \
PIN_OSPEED_100M(GPIOE_MEM_D11) | \
PIN_OSPEED_100M(GPIOE_MEM_D12))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_SRAM_LB) | \
PIN_PUPDR_PULLUP(GPIOE_SRAM_UB) | \
PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D4) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D5) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D6) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D7) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D8) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D9) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D10) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D11) | \
PIN_PUPDR_PULLUP(GPIOE_MEM_D12))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_SRAM_LB) | \
PIN_PUPDR_FLOATING(GPIOE_SRAM_UB) | \
PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D4) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D5) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D6) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D7) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D8) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D9) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D10) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D11) | \
PIN_PUPDR_FLOATING(GPIOE_MEM_D12))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_SRAM_LB) | \
PIN_ODR_HIGH(GPIOE_SRAM_UB) | \
PIN_ODR_HIGH(GPIOE_PIN2) | \
@ -784,22 +784,22 @@
PIN_OSPEED_100M(GPIOF_MEM_A7) | \
PIN_OSPEED_100M(GPIOF_MEM_A8) | \
PIN_OSPEED_100M(GPIOF_MEM_A9))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_MEM_A0) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A1) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A2) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A3) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A4) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A5) | \
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A6) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A7) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A8) | \
PIN_PUPDR_PULLUP(GPIOF_MEM_A9))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_MEM_A0) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A1) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A2) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A3) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A4) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A5) | \
PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A6) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A7) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A8) | \
PIN_PUPDR_FLOATING(GPIOF_MEM_A9))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_MEM_A0) | \
PIN_ODR_HIGH(GPIOF_MEM_A1) | \
PIN_ODR_HIGH(GPIOF_MEM_A2) | \
@ -890,22 +890,22 @@
#else
#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
#endif
#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_MEM_A10) | \
PIN_PUPDR_PULLUP(GPIOG_MEM_A11) | \
PIN_PUPDR_PULLUP(GPIOG_MEM_A12) | \
PIN_PUPDR_PULLUP(GPIOG_MEM_A13) | \
PIN_PUPDR_PULLUP(GPIOG_MEM_A14) | \
PIN_PUPDR_PULLUP(GPIOG_MEM_A15) | \
#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \
NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_RB2) | \
PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \
PIN_PUPDR_PULLUP(GPIOG_PIN10) | \
PIN_PUPDR_PULLUP(GPIOG_PIN11) | \
PIN_PUPDR_PULLUP(GPIOG_SRAM_CS1) | \
PIN_PUPDR_PULLUP(GPIOG_PIN13) | \
PIN_PUPDR_PULLUP(GPIOG_PIN14) | \
PIN_PUPDR_PULLUP(GPIOG_PIN15))
PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
PIN_PUPDR_FLOATING(GPIOG_NAND_CE2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \
PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
PIN_PUPDR_FLOATING(GPIOG_PIN15))
#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_MEM_A10) | \
PIN_ODR_HIGH(GPIOG_MEM_A11) | \
PIN_ODR_HIGH(GPIOG_MEM_A12) | \

9
testhal/STM32/STM32F4xx/FSMC_SRAM/main.c
View File

@ -62,7 +62,7 @@ static const size_t sram_size = 524288;
* SRAM driver configuration structure.
*/
static const SRAMConfig sram_cfg = {
.btr = 2 << 8 | 1
.btr = 2 << 8
};
/* benchmarking results in MiB/S */
@ -90,7 +90,7 @@ static void sram_benchmark(void){
chTMObjectInit(&mem_tmu);
chTMStartMeasurementX(&mem_tmu);
memset(sram_start, 0x55, sram_size);
memset(sram_start, 0xAA, sram_size);
memset(sram_start, 0x00, sram_size);
chTMStopMeasurementX(&mem_tmu);
memset_speed_ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
@ -106,15 +106,16 @@ static void sram_benchmark(void){
chTMObjectInit(&mem_tmu);
chTMStartMeasurementX(&mem_tmu);
for (i=0; i<16; i++)
memcpy(sram_check_buf, sram_start, sizeof(sram_check_buf));
memcpy(sram_check_buf, sram_start+ i * sizeof(sram_check_buf), sizeof(sram_check_buf));
chTMStopMeasurementX(&mem_tmu);
memcpy_speed_ext2int = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
/* memcpy int2ext */
chTMObjectInit(&mem_tmu);
memset(sram_check_buf, 0xAA, sizeof(sram_check_buf));
chTMStartMeasurementX(&mem_tmu);
for (i=0; i<16; i++)
memcpy(sram_start, sram_check_buf, sizeof(sram_check_buf));
memcpy(sram_start + i * sizeof(sram_check_buf), sram_check_buf, sizeof(sram_check_buf));
chTMStopMeasurementX(&mem_tmu);
memcpy_speed_int2ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
}