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ChibiOS
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Improved clock checks. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14397 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-19 16:01:33 +00:00
parent 82d461b66d
commit 2cd2b4dfad
2 changed files with 52 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
View File

@ -631,15 +631,8 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) { if (&ADCD1 == adcp) {
#if defined(STM32_ADC12_CLOCK) osalDbgAssert(STM32_ADC1_CLOCK <= STM32_ADCCLK_MAX,
osalDbgAssert(STM32_ADC12_CLOCK <= STM32_ADCCLK_MAX,
"invalid clock frequency"); "invalid clock frequency");
#elif defined(STM32_ADC123_CLOCK)
osalDbgAssert(STM32_ADC123_CLOCK <= STM32_ADCCLK_MAX,
"invalid clock frequency");
#else
#error "missing clock macro"
#endif
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM, adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY, STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
@ -666,7 +659,7 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2 #if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) { if (&ADCD2 == adcp) {
osalDbgAssert(STM32_ADC12_CLOCK <= STM32_ADCCLK_MAX, osalDbgAssert(STM32_ADC2_CLOCK <= STM32_ADCCLK_MAX,
"invalid clock frequency"); "invalid clock frequency");
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM, adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM,
@ -694,7 +687,7 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3 #if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) { if (&ADCD3 == adcp) {
osalDbgAssert(STM32_ADC345_CLOCK <= STM32_ADCCLK_MAX, osalDbgAssert(STM32_ADC3_CLOCK <= STM32_ADCCLK_MAX,
"invalid clock frequency"); "invalid clock frequency");
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM, adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM,
@ -725,7 +718,7 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC4 #if STM32_ADC_USE_ADC4
if (&ADCD4 == adcp) { if (&ADCD4 == adcp) {
osalDbgAssert(STM32_ADC345_CLOCK <= STM32_ADCCLK_MAX, osalDbgAssert(STM32_ADC4_CLOCK <= STM32_ADCCLK_MAX,
"invalid clock frequency"); "invalid clock frequency");
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC4_DMA_STREAM, adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC4_DMA_STREAM,

68
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
View File

@ -709,25 +709,33 @@
/* ADC clock source checks.*/ /* ADC clock source checks.*/
#if defined(STM32F3XX) #if defined(STM32F3XX)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC12_CLOCK STM32_ADC12CLK #define STM32_ADC1_CLOCK STM32_ADC12CLK
#define STM32_ADC2_CLOCK STM32_ADC12CLK
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC12_CLOCK (STM32_HCLK / 1) #define STM32_ADC1_CLOCK (STM32_HCLK / 1)
#define STM32_ADC2_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC12_CLOCK (STM32_HCLK / 2) #define STM32_ADC1_CLOCK (STM32_HCLK / 2)
#define STM32_ADC2_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC12_CLOCK (STM32_HCLK / 4) #define STM32_ADC1_CLOCK (STM32_HCLK / 4)
#define STM32_ADC2_CLOCK (STM32_HCLK / 4)
#else #else
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif #endif
#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC34_CLOCK STM32_ADC34CLK #define STM32_ADC3_CLOCK STM32_ADC34CLK
#define STM32_ADC4_CLOCK STM32_ADC34CLK
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC34_CLOCK (STM32_HCLK / 1) #define STM32_ADC3_CLOCK (STM32_HCLK / 1)
#define STM32_ADC4_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 #elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC34_CLOCK (STM32_HCLK / 2) #define STM32_ADC3_CLOCK (STM32_HCLK / 2)
#define STM32_ADC4_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 #elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC34_CLOCK (STM32_HCLK / 4) #define STM32_ADC3_CLOCK (STM32_HCLK / 4)
#define STM32_ADC4_CLOCK (STM32_HCLK / 4)
#else #else
#error "invalid clock mode selected for STM32_ADC_ADC34_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC34_CLOCK_MODE"
#endif #endif
@ -735,13 +743,21 @@
#if defined(STM32L4XX) || defined(STM32L4XXP) #if defined(STM32L4XX) || defined(STM32L4XXP)
#if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC123_CLOCK (STM32_ADCCLK / ADC123_PRESC_VALUE) #define STM32_ADC1_CLOCK (STM32_ADCCLK / ADC123_PRESC_VALUE)
#define STM32_ADC2_CLOCK (STM32_ADCCLK / ADC123_PRESC_VALUE)
#define STM32_ADC3_CLOCK (STM32_ADCCLK / ADC123_PRESC_VALUE)
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC123_CLOCK (STM32_ADCCLK / 1) #define STM32_ADC1_CLOCK (STM32_ADCCLK / 1)
#define STM32_ADC2_CLOCK (STM32_ADCCLK / 1)
#define STM32_ADC3_CLOCK (STM32_ADCCLK / 1)
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC123_CLOCK (STM32_ADCCLK / 2) #define STM32_ADC1_CLOCK (STM32_ADCCLK / 2)
#define STM32_ADC2_CLOCK (STM32_ADCCLK / 2)
#define STM32_ADC3_CLOCK (STM32_ADCCLK / 2)
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC123_CLOCK (STM32_ADCCLK / 4) #define STM32_ADC1_CLOCK (STM32_ADCCLK / 4)
#define STM32_ADC2_CLOCK (STM32_ADCCLK / 4)
#define STM32_ADC3_CLOCK (STM32_ADCCLK / 4)
#else #else
#error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE"
#endif #endif
@ -749,25 +765,37 @@
#if defined(STM32G4XX) #if defined(STM32G4XX)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC12_CLOCK (STM32_ADC12CLK / ADC12_PRESC_VALUE) #define STM32_ADC1_CLOCK (STM32_ADC12CLK / ADC12_PRESC_VALUE)
#define STM32_ADC2_CLOCK (STM32_ADC12CLK / ADC12_PRESC_VALUE)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC12_CLOCK (STM32_HCLK / 1) #define STM32_ADC1_CLOCK (STM32_HCLK / 1)
#define STM32_ADC2_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC12_CLOCK (STM32_HCLK / 2) #define STM32_ADC1_CLOCK (STM32_HCLK / 2)
#define STM32_ADC2_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC12_CLOCK (STM32_HCLK / 4) #define STM32_ADC1_CLOCK (STM32_HCLK / 4)
#define STM32_ADC2_CLOCK (STM32_HCLK / 4)
#else #else
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif #endif
#if STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC345_CLOCK (STM32_ADC345CLK / ADC345_PRESC_VALUE) #define STM32_ADC3_CLOCK (STM32_ADC345CLK / ADC345_PRESC_VALUE)
#define STM32_ADC4_CLOCK (STM32_ADC345CLK / ADC345_PRESC_VALUE)
#define STM32_ADC5_CLOCK (STM32_ADC345CLK / ADC345_PRESC_VALUE)
#elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC345_CLOCK (STM32_HCLK / 1) #define STM32_ADC3_CLOCK (STM32_HCLK / 1)
#define STM32_ADC4_CLOCK (STM32_HCLK / 1)
#define STM32_ADC5_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 #elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC345_CLOCK (STM32_HCLK / 2) #define STM32_ADC3_CLOCK (STM32_HCLK / 2)
#define STM32_ADC4_CLOCK (STM32_HCLK / 2)
#define STM32_ADC5_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 #elif STM32_ADC_ADC345_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC345_CLOCK (STM32_HCLK / 4) #define STM32_ADC3_CLOCK (STM32_HCLK / 4)
#define STM32_ADC4_CLOCK (STM32_HCLK / 4)
#define STM32_ADC5_CLOCK (STM32_HCLK / 4)
#else #else
#error "invalid clock mode selected for STM32_ADC_ADC345_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC345_CLOCK_MODE"
#endif #endif