From 2d4e29da76f6357bb735e13f59f2708433983593 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 15 May 2021 17:08:09 +0000 Subject: [PATCH] More common BD code. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14380 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32G0xx/hal_lld.c | 39 +------------------------ os/hal/ports/STM32/STM32L4xx+/hal_lld.c | 39 +------------------------ os/hal/ports/STM32/STM32L4xx/hal_lld.c | 39 +------------------------ os/hal/ports/STM32/STM32L5xx/hal_lld.c | 39 +------------------------ 4 files changed, 4 insertions(+), 152 deletions(-) diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.c b/os/hal/ports/STM32/STM32G0xx/hal_lld.c index 22b71a66c..d662aa721 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.c @@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Resets the backup domain. - */ -__STATIC_INLINE void bd_reset(void) { - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0U; - } -} - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing RTC clock source impossible without reset - * of the whole BKP domain. - */ -__STATIC_INLINE void bd_init(void) { - uint32_t bdcr; - - /* Current settings.*/ - bdcr = RCC->BDCR; - -#if HAL_USE_RTC - /* RTC clock enabled.*/ - if ((bdcr & RCC_BDCR_RTCEN) == 0) { - bdcr |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - - /* Selectors.*/ - bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK); - bdcr |= STM32_RTCSEL | STM32_LSCOSEL; - - /* Final settings.*/ - RCC->BDCR = bdcr; -} +#include "stm32_bd.inc" /*===========================================================================*/ /* Driver interrupt handlers. */ diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c index 0edb4bafa..54cf3cf93 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c @@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Resets the backup domain. - */ -__STATIC_INLINE void bd_reset(void) { - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0U; - } -} - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing RTC clock source impossible without reset - * of the whole BKP domain. - */ -__STATIC_INLINE void bd_init(void) { - uint32_t bdcr; - - /* Current settings.*/ - bdcr = RCC->BDCR; - -#if HAL_USE_RTC - /* RTC clock enabled.*/ - if ((bdcr & RCC_BDCR_RTCEN) == 0) { - bdcr |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - - /* Selectors.*/ - bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK); - bdcr |= STM32_RTCSEL | STM32_LSCOSEL; - - /* Final settings.*/ - RCC->BDCR = bdcr; -} +#include "stm32_bd.inc" /*===========================================================================*/ /* Driver interrupt handlers. */ diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index 7034736f2..1dc6d34b1 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Resets the backup domain. - */ -__STATIC_INLINE void bd_reset(void) { - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0U; - } -} - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing RTC clock source impossible without reset - * of the whole BKP domain. - */ -__STATIC_INLINE void bd_init(void) { - uint32_t bdcr; - - /* Current settings.*/ - bdcr = RCC->BDCR; - -#if HAL_USE_RTC - /* RTC clock enabled.*/ - if ((bdcr & RCC_BDCR_RTCEN) == 0) { - bdcr |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - - /* Selectors.*/ - bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK); - bdcr |= STM32_RTCSEL | STM32_LSCOSEL; - - /* Final settings.*/ - RCC->BDCR = bdcr; -} +#include "stm32_bd.inc" /*===========================================================================*/ /* Driver interrupt handlers. */ diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.c b/os/hal/ports/STM32/STM32L5xx/hal_lld.c index bbf7b9d7c..ce9c4862c 100644 --- a/os/hal/ports/STM32/STM32L5xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.c @@ -52,44 +52,7 @@ uint32_t SystemCoreClock = STM32_HCLK; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Resets the backup domain. - */ -__STATIC_INLINE void bd_reset(void) { - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0U; - } -} - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing RTC clock source impossible without reset - * of the whole BKP domain. - */ -__STATIC_INLINE void bd_init(void) { - uint32_t bdcr; - - /* Current settings.*/ - bdcr = RCC->BDCR; - -#if HAL_USE_RTC - /* RTC enable.*/ - if ((bdcr & RCC_BDCR_RTCEN) == 0U) { - bdcr |= RCC_BDCR_RTCEN; - } -#endif - - /* Selectors.*/ - bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK); - bdcr |= STM32_RTCSEL | STM32_LSCOSEL; - - /* Final settings.*/ - RCC->BDCR = bdcr; -} +#include "stm32_bd.inc" __STATIC_INLINE void flash_ws_init(uint32_t bits) {