I2C. Bug fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3562 35acf78f-673a-0410-8e92-d51de3d6d3f4
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barthess
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d34bc423c8
commit
2db3c769f1
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@ -141,6 +141,16 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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dp->DR = i2cp->slave_addr;
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break;
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case I2C_EV6_MASTER_REC_MODE_SELECTED:
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dmaStreamEnable(i2cp->dmarx);
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i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST;
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break;
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case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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dmaStreamEnable(i2cp->dmatx);
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i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST;
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break;
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case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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/* catch BTF event after the end of trasmission */
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if (i2cp->rxbytes > 1){
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@ -197,6 +207,14 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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i2cflags_t flags;
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I2C_TypeDef *reg;
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chSysLockFromIsr();
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/* clear interrupt falgs just to be safe */
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dmaStreamClearInterrupt(i2cp->dmatx);
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dmaStreamClearInterrupt(i2cp->dmarx);
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dmaStreamDisable(i2cp->dmatx);
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dmaStreamDisable(i2cp->dmarx);
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chSysUnlockFromIsr();
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reg = i2cp->id_i2c;
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flags = I2CD_NO_ERROR;
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@ -481,9 +499,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr,
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dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
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dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
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dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode));
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dmaStreamEnable(i2cp->dmarx);
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i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST;
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i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN;
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i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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}
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@ -521,9 +537,7 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr,
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dmaStreamSetMemory0(i2cp->dmatx, txbuf);
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dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
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dmaStreamSetMode(i2cp->dmatx, ((i2cp->dmamode) | mode));
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dmaStreamEnable(i2cp->dmatx);
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i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST;
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i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN;
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i2cp->id_i2c->CR1 |= I2C_CR1_START;
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}
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@ -171,12 +171,15 @@
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/** @brief flags for interrupt handling */
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#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */
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#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */
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#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
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#define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */
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#define I2C_FLG_MASTER_RECEIVER 0x10
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#define I2C_FLG_HEADER_SENT 0x80
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/** @brief error checks */
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#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
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#error "I2C1 not present in the selected device"
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#endif
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@ -197,57 +200,39 @@
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 RX"
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#error "invalid DMA stream associated to I2C1 RX"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 TX"
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#error "invalid DMA stream associated to I2C1 TX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 RX"
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#error "invalid DMA stream associated to I2C2 RX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 TX"
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#error "invalid DMA stream associated to I2C2 TX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \
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STM32_I2C3_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 RX"
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#error "invalid DMA stream associated to I2C3 RX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 TX"
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#error "invalid DMA stream associated to I2C3 TX"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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@ -300,22 +285,22 @@ struct I2CDriver{
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/**
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* @brief Driver state.
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*/
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i2cstate_t id_state;
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i2cstate_t id_state;
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#if I2C_USE_WAIT
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/**
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* @brief Thread waiting for I/O completion.
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*/
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Thread *id_thread;
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Thread *id_thread;
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#endif /* I2C_USE_WAIT */
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#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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Mutex id_mutex;
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Mutex id_mutex;
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#elif CH_USE_SEMAPHORES
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Semaphore id_semaphore;
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Semaphore id_semaphore;
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#endif
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#endif /* I2C_USE_MUTUAL_EXCLUSION */
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@ -338,17 +323,13 @@ struct I2CDriver{
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uint8_t slave_addr; /*!< @brief Current slave address without R/W bit. */
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#if CH_USE_EVENTS
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EventSource sevent; /*!< @brief Status Change @p EventSource.*/
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#endif
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/*********** End of the mandatory fields. **********************************/
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uint32_t dmamode; /*!< @brief DMA mode bit mask.*/
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const stm32_dma_stream_t *dmarx; /*!< @brief Receive DMA channel.*/
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const stm32_dma_stream_t *dmatx; /*!< @brief Transmit DMA channel.*/
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I2C_TypeDef *id_i2c; /*!< @brief Pointer to the I2Cx registers block. */
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I2C_TypeDef *id_i2c; /*!< @brief Pointer to the I2Cx registers block. */
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};
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@ -292,15 +292,16 @@
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) | \
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STM32_DMA_STREAM_ID_MSK(1, 5)))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) | \
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(STM32_DMA_STREAM_ID_MSK(1, 6)))
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#define STM32_I2C1_TX_DMA_CHN 0x10000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) | \
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STM32_DMA_STREAM_ID_MSK(1, 3)))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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@ -238,7 +238,6 @@ void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask) {
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chDbgCheck(i2cp != NULL, "i2cAddFlagsI");
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i2cp->errors |= mask;
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chEvtBroadcastI(&i2cp->sevent);
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}
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/**
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