STM32F4 clock tree rework, unfinished.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12022 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio
parent
d7921befb0
commit
2dbd8fea1a
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@ -30,7 +30,7 @@
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* - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,
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* STM32F446xx for High-performance STM32F4 devices of
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* Foundation line.
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* - STM32F401xC, STM32F401xE, STM32F410Cx, STM32F410Rx, STM32F411xE
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* - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx
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* for High-performance STM32F4 devices of Access line.
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* - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
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* STM32F479xx for High-performance STM32F4 devices of Advanced line.
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@ -447,13 +447,11 @@
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#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */
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#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
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#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
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#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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#if defined(STM32F413xx)
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#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
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#define STM32_PLLI2SSRC_CKIN (0 << 22) /**< PLLI2SSRC is CK_IN. */
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#define STM32_PLLI2SSRC_I2SCKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
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#endif
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#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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/** @} */
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/**
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@ -535,34 +533,19 @@
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* @{
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*/
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#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
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#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is PCLK1. */
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#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
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#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
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#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
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#if defined(STM32F413xx)
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/* TODO: Chibios definition could be set from CMSIS stm32f413xx.h. */
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#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
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#define STM32_I2CFMP1SEL_APB (0 << 22) /**< I2C1 source is APB. */
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#define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
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#define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
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#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
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#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
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#define STM32_LPTIM1SEL_HSI (1 << 30) /**< LPTIM1 source is HSI. */
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#define STM32_LPTIM1SEL_LSI (2 << 30) /**< LPTIM1 source is LSI. */
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#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
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#endif
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#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
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#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
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#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
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#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
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#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
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#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
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#if defined(STM32F413xx)
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#define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */
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#endif
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#define STM32_CK48MSEL_PLLALT (1 << 27) /**< PLL48CLK source is PLLSAI
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or PLLI2S depending on
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device. */
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#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
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#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
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@ -571,6 +554,12 @@
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#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
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#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
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#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
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#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
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#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
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#define STM32_LPTIM1SEL_HSI (1 << 30) /**< LPTIM1 source is HSI. */
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#define STM32_LPTIM1SEL_LSI (2 << 30) /**< LPTIM1 source is LSI. */
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#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
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/** @} */
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/*===========================================================================*/
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@ -1447,7 +1436,9 @@
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/*
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* PLL enable check.
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*/
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#if STM32_CLOCK48_REQUIRED || \
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#if (STM32_CLOCK48_REQUIRED && \
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STM32_HAS_RCC_CK48MSEL && \
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(STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
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(STM32_SW == STM32_SW_PLL) || \
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(STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
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(STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
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@ -1681,11 +1672,14 @@
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/*
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* PLLI2S enable check.
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*/
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#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S) \
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&& defined(STM32F413xx)) || \
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(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S) || \
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#if (STM32_HAS_RCC_PLLI2S && \
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STM32_CLOCK48_REQUIRED && \
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(STM32_HAS_RCC_CK48MSEL && \
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STM32_RCC_CK48MSEL_USES_I2S && \
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(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
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(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) || \
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defined(__DOXYGEN__)
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/**
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@ -1812,11 +1806,14 @@
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/*
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* PLLSAI enable check.
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*/
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#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI) \
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&& defined(STM32F446xx)) || \
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(STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
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#if (STM32_HAS_RCC_PLLSAI && \
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STM32_CLOCK48_REQUIRED && \
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(STM32_HAS_RCC_CK48MSEL && \
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!STM32_RCC_CK48MSEL_USES_I2S && \
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(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
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(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI)) || \
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defined(__DOXYGEN__)
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/**
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* @brief PLLSAI activation flag.
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@ -2060,15 +2057,21 @@
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* @brief 48MHz frequency.
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*/
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#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
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#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
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#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
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#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#elif (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI) && defined(STM32F446xx)
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#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
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#elif (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S) && defined(STM32F413xx)
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#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
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#if STM32_RCC_CK48MSEL_USES_I2S
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#define STM32_PLL48CLK STM32_PLLI2S_Q_CLKOUT
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#else
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#define STM32_PLL48CLK STM32_PLLSAI_Q_CLKOUT
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#endif
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#else
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#error "invalid source selected for PLL48CLK clock"
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#endif
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#else /* !STM32_HAS_RCC_CK48MSEL */
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#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#endif /* !STM32_HAS_RCC_CK48MSEL */
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#else /* !STM32_CLOCK48_REQUIRED */
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#define STM32_PLL48CLK 0
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#endif /* STM32_CLOCK48_REQUIRED */
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@ -90,9 +90,12 @@
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#if defined(STM32F469_479xx) || defined(__DOXYGEN__)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL TRUE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI TRUE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_I2SSRC TRUE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL TRUE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -466,9 +469,12 @@
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#if defined(STM32F446xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL TRUE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI TRUE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_I2SSRC FALSE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL TRUE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -817,9 +823,14 @@
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL TRUE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI TRUE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
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#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
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#define STM32_HAS_RCC_I2SSRC TRUE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL FALSE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -1183,15 +1194,18 @@
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#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
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/*===========================================================================*/
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/* STM32F413xx, STM32F413Mx, STM32F413Rx, STM32F413Vx, STM32F413Zx */
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/* STM32F413xx. */
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/*===========================================================================*/
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#if defined(STM32F413xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_I2SSRC FALSE
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#define STM32_HAS_RCC_I2SPLLSRC TRUE
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#define STM32_HAS_RCC_CK48MSEL TRUE
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#define STM32_RCC_CK48MSEL_USES_I2S TRUE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -1561,15 +1575,18 @@
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#endif /* defined(STM32F413xx) */
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/*===========================================================================*/
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/* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx */
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/* STM32F412xx. */
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/*===========================================================================*/
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#if defined(STM32F412xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_I2SSRC FALSE
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#define STM32_HAS_RCC_I2SPLLSRC TRUE
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#define STM32_HAS_RCC_CK48MSEL TRUE
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#define STM32_RCC_CK48MSEL_USES_I2S TRUE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -1890,15 +1907,18 @@
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#endif /* defined(STM32F412xx) */
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/*===========================================================================*/
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/* STM32F411xC, STM32F411xE */
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/* STM32F411xx. */
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/*===========================================================================*/
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#if defined(STM32F411xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_I2SSRC TRUE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL FALSE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -2193,15 +2213,20 @@
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#endif /* defined(STM32F411xx) */
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/*===========================================================================*/
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/* STM32F410Cx, STM32F410Rx. */
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/* STM32F410xx. */
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/*===========================================================================*/
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#if defined(STM32F410xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL FALSE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S FALSE
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#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
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#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
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#define STM32_HAS_RCC_I2SSRC FALSE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL FALSE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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@ -2465,16 +2490,21 @@
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#endif /* defined(STM32F410xx) */
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/*===========================================================================*/
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/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */
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/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx, */
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/* STM32F215xx, STM32F207xx, STM32F217xx. */
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/*===========================================================================*/
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#if defined(STM32F40_41xxx) || defined(STM32F2XX)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL TRUE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S TRUE
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#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
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#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
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#define STM32_HAS_RCC_I2SSRC TRUE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL FALSE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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#if defined(STM32F401xx)
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/* Clock tree attributes.*/
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#define STM32_HAS_RCC_SAIPLL FALSE
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#define STM32_HAS_RCC_I2CPLL FALSE
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#define STM32_HAS_RCC_PLLSAI FALSE
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#define STM32_HAS_RCC_PLLI2S FALSE
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#define STM32_HAS_RCC_I2SSRC FALSE
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#define STM32_HAS_RCC_I2SPLLSRC FALSE
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#define STM32_HAS_RCC_CK48MSEL FALSE
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#define STM32_RCC_CK48MSEL_USES_I2S FALSE
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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