andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5428 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
acirillo87 2013-03-14 15:13:57 +00:00
parent 26928f601f
commit 2f5f9bd380
6 changed files with 649 additions and 740 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

567
os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
View File

File diff suppressed because it is too large Load Diff

166
os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
View File

@ -20,6 +20,8 @@
* @{
*/
#include "spc5_flexpwm.h"
#ifndef _PWM_LLD_H_
#define _PWM_LLD_H_
@ -46,163 +48,18 @@
#define SPC5_FLEXPWM_STS_RUF (1U << 14)
/** @} */
/**
* @name CTRL2 register bits definitions
* @{
*/
#define SPC5_FLEXPWM_CNTL2_CLKSEL0 (1U << 0)
#define SPC5_FLEXPWM_CNTL2_CLKSEL1 (1U << 1)
#define SPC5_FLEXPWM_CNTL2_RELOAD_SEL (1U << 2)
#define SPC5_FLEXPWM_CNTL2_FORCE_SEL0 (1U << 3)
#define SPC5_FLEXPWM_CNTL2_FORCE_SEL1 (1U << 4)
#define SPC5_FLEXPWM_CNTL2_FORCE_SEL2 (1U << 5)
#define SPC5_FLEXPWM_CNTL2_FORCE (1U << 6)
#define SPC5_FLEXPWM_CNTL2_FRCEN (1U << 7)
#define SPC5_FLEXPWM_CNTL2_INIT_SEL0 (1U << 8)
#define SPC5_FLEXPWM_CNTL2_INIT_SEL1 (1U << 9)
#define SPC5_FLEXPWM_CNTL2_PWM_X_INIT (1U << 10)
#define SPC5_FLEXPWM_CNTL2_PWM_B_INIT (1U << 11)
#define SPC5_FLEXPWM_CNTL2_PWM_A_INIT (1U << 12)
#define SPC5_FLEXPWM_CNTL2_INDEP (1U << 13)
#define SPC5_FLEXPWM_CNTL2_WAITEN (1U << 14)
#define SPC5_FLEXPWM_CNTL2_DGBEN (1U << 15)
/** @} */
/**
* @name CTRL1 register bits definitions
* @{
*/
#define SPC5_FLEXPWM_CNTL1_DBLEN (1U << 0)
#define SPC5_FLEXPWM_CNTL1_PRSC0 (1U << 4)
#define SPC5_FLEXPWM_CNTL1_PRSC1 (1U << 5)
#define SPC5_FLEXPWM_CNTL1_PRSC2 (1U << 6)
#define SPC5_FLEXPWM_CNTL1_FULL (1U << 10)
#define SPC5_FLEXPWM_CNTL1_HALF (1U << 11)
#define SPC5_FLEXPWM_CNTL1_LDFQ0 (1U << 12)
#define SPC5_FLEXPWM_CNTL1_LDFQ1 (1U << 13)
#define SPC5_FLEXPWM_CNTL1_LDFQ2 (1U << 14)
#define SPC5_FLEXPWM_CNTL1_LDFQ3 (1U << 15)
/** @} */
/**
* @name OCTRL register bits definitions
* @{
*/
#define SPC5_FLEXPWM_OCNTL_PWMXFS0 (1U << 0)
#define SPC5_FLEXPWM_OCNTL_PWMXFS1 (1U << 1)
#define SPC5_FLEXPWM_OCNTL_PWMBFS0 (1U << 2)
#define SPC5_FLEXPWM_OCNTL_PWMBFS1 (1U << 3)
#define SPC5_FLEXPWM_OCNTL_PWMAFS0 (1U << 4)
#define SPC5_FLEXPWM_OCNTL_PWMAFS1 (1U << 5)
#define SPC5_FLEXPWM_OCNTL_POLX (1U << 8)
#define SPC5_FLEXPWM_OCNTL_POLB (1U << 9)
#define SPC5_FLEXPWM_OCNTL_POLA (1U << 10)
#define SPC5_FLEXPWM_OCNTL_PWMX_IN (1U << 13)
#define SPC5_FLEXPWM_OCNTL_PWMB_IN (1U << 14)
#define SPC5_FLEXPWM_OCNTL_PWMA_IN (1U << 15)
/** @} */
/**
* @name INTEN register bits definitions
* @{
*/
#define SPC5_FLEXPWM_INTEN_CMPIE0 (1U << 0)
#define SPC5_FLEXPWM_INTEN_CMPIE1 (1U << 1)
#define SPC5_FLEXPWM_INTEN_CMPIE2 (1U << 2)
#define SPC5_FLEXPWM_INTEN_CMPIE3 (1U << 3)
#define SPC5_FLEXPWM_INTEN_CMPIE4 (1U << 4)
#define SPC5_FLEXPWM_INTEN_CMPIE5 (1U << 5)
#define SPC5_FLEXPWM_INTEN_CX0IE (1U << 6)
#define SPC5_FLEXPWM_INTEN_CX1IE (1U << 7)
#define SPC5_FLEXPWM_INTEN_RIE (1U << 12)
#define SPC5_FLEXPWM_INTEN_REIE (1U << 13)
/** @} */
/**
* @name OUTEN register bits definitions
* @{
*/
#define SPC5_FLEXPWM_OUTEN_PWMX_EN0 (1U << 0)
#define SPC5_FLEXPWM_OUTEN_PWMX_EN1 (1U << 1)
#define SPC5_FLEXPWM_OUTEN_PWMX_EN2 (1U << 2)
#define SPC5_FLEXPWM_OUTEN_PWMX_EN3 (1U << 3)
#define SPC5_FLEXPWM_OUTEN_PWMB_EN0 (1U << 4)
#define SPC5_FLEXPWM_OUTEN_PWMB_EN1 (1U << 5)
#define SPC5_FLEXPWM_OUTEN_PWMB_EN2 (1U << 6)
#define SPC5_FLEXPWM_OUTEN_PWMB_EN3 (1U << 7)
#define SPC5_FLEXPWM_OUTEN_PWMA_EN0 (1U << 8)
#define SPC5_FLEXPWM_OUTEN_PWMA_EN1 (1U << 9)
#define SPC5_FLEXPWM_OUTEN_PWMA_EN2 (1U << 10)
#define SPC5_FLEXPWM_OUTEN_PWMA_EN3 (1U << 11)
/** @} */
/**
* @name MASK register bits definitions
* @{
*/
#define SPC5_FLEXPWM_MASK_MASKX0 (1U << 0)
#define SPC5_FLEXPWM_MASK_MASKX1 (1U << 1)
#define SPC5_FLEXPWM_MASK_MASKX2 (1U << 2)
#define SPC5_FLEXPWM_MASK_MASKX3 (1U << 3)
#define SPC5_FLEXPWM_MASK_MASKB0 (1U << 4)
#define SPC5_FLEXPWM_MASK_MASKB1 (1U << 5)
#define SPC5_FLEXPWM_MASK_MASKB2 (1U << 6)
#define SPC5_FLEXPWM_MASK_MASKB3 (1U << 7)
#define SPC5_FLEXPWM_MASK_MASKA0 (1U << 8)
#define SPC5_FLEXPWM_MASK_MASKA1 (1U << 9)
#define SPC5_FLEXPWM_MASK_MASKA2 (1U << 10)
#define SPC5_FLEXPWM_MASK_MASKA3 (1U << 11)
/** @} */
/**
* @name MCTRL register bits definitions
* @{
*/
#define SPC5_FLEXPWM_MCTRL_LDOK0 (1U << 0)
#define SPC5_FLEXPWM_MCTRL_LDOK1 (1U << 1)
#define SPC5_FLEXPWM_MCTRL_LODK2 (1U << 2)
#define SPC5_FLEXPWM_MCTRL_LDOK3 (1U << 3)
#define SPC5_FLEXPWM_MCTRL_CLDOK0 (1U << 4)
#define SPC5_FLEXPWM_MCTRL_CLDOK1 (1U << 5)
#define SPC5_FLEXPWM_MCTRL_CLDOK2 (1U << 6)
#define SPC5_FLEXPWM_MCTRL_CLDOK3 (1U << 7)
#define SPC5_FLEXPWM_MCTRL_RUN0 (1U << 8)
#define SPC5_FLEXPWM_MCTRL_RUN1 (1U << 9)
#define SPC5_FLEXPWM_MCTRL_RUN2 (1U << 10)
#define SPC5_FLEXPWM_MCTRL_RUN3 (1U << 11)
#define SPC5_FLEXPWM_MCTRL_IPOL0 (1U << 12)
#define SPC5_FLEXPWM_MCTRL_IPOL1 (1U << 13)
#define SPC5_FLEXPWM_MCTRL_IPOL2 (1U << 14)
#define SPC5_FLEXPWM_MCTRL_IPOL3 (1U << 15)
/** @} */
/**
* @name PSC values definition
* @{
*/
#define SPC5_FLEXPWM_PSC_1 0
#define SPC5_FLEXPWM_PSC_2 SPC5_FLEXPWM_CNTL1_PRSC0
#define SPC5_FLEXPWM_PSC_4 SPC5_FLEXPWM_CNTL1_PRSC1
#define SPC5_FLEXPWM_PSC_8 SPC5_FLEXPWM_CNTL1_PRSC0 || \
SPC5_FLEXPWM_CNTL1_PRSC1
#define SPC5_FLEXPWM_PSC_16 SPC5_FLEXPWM_CNTL1_PRSC2
#define SPC5_FLEXPWM_PSC_32 SPC5_FLEXPWM_CNTL1_PRSC0 || \
SPC5_FLEXPWM_CNTL1_PRSC2
#define SPC5_FLEXPWM_PSC_64 SPC5_FLEXPWM_CNTL1_PRSC1 || \
SPC5_FLEXPWM_CNTL1_PRSC2
#define SPC5_FLEXPWM_PSC_128 SPC5_FLEXPWM_CNTL1_PRSC0 || \
SPC5_FLEXPWM_CNTL1_PRSC1 || \
SPC5_FLEXPWM_CNTL1_PRSC2
/** @} */
/**
* @name LDOK, CLDOK, RUN, IPOL masks definition
* @{
*/
#define SPC5_FLEXPWM_LDOK_MASK 0x000F
#define SPC5_FLEXPWM_CLDOK_MASK 0x00F0
#define SPC5_FLEXPWM_RUN_MASK 0x0F00
#define SPC5_FLEXPWM_IPOL_MASK 0xF000
#define SPC5_FLEXPWM_PSC_1 0U
#define SPC5_FLEXPWM_PSC_2 1U
#define SPC5_FLEXPWM_PSC_4 2U
#define SPC5_FLEXPWM_PSC_8 3U
#define SPC5_FLEXPWM_PSC_16 4U
#define SPC5_FLEXPWM_PSC_32 5U
#define SPC5_FLEXPWM_PSC_64 6U
#define SPC5_FLEXPWM_PSC_128 7U
/** @} */
/**
@ -479,10 +336,9 @@
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
#include "flexpwm.h"
/**
* @brief PWM mode type.
* @brief PWM mode type.
*/
typedef uint32_t pwmmode_t;

0
os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h → os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h
View File

514
os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
View File

@ -181,6 +181,13 @@ ICUDriver ICUD18;
/* Driver local variables. */
/*===========================================================================*/
/**
* @brief Number of active eTimer Submodules.
*/
static uint32_t icu_active_submodules0;
static uint32_t icu_active_submodules1;
static uint32_t icu_active_submodules2;
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@ -201,9 +208,11 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
_icu_isr_invoke_overflow_cb(icup);
}
if ((sr & 0x0040) != 0) { /* ICF1 */
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE == 0b011) {
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
SPC5_ETIMER_CNTMODE_RFE_SIHA) {
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = 0b001;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
SPC5_ETIMER_CNTMODE_RE;
}
else {
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
@ -212,7 +221,8 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
}
}
else if ((sr & 0x0080) != 0) { /* ICF2 */
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE == 0b011) {
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
SPC5_ETIMER_CNTMODE_RFE_SIHA) {
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0x0000;
}
@ -257,62 +267,76 @@ static void spc5_icu_smod_init(ICUDriver *icup) {
/* Set primary source and clock prescaler.*/
switch (psc) {
case 1:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11000;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1;
break;
case 2:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11001;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2;
break;
case 4:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11010;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4;
break;
case 8:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11011;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8;
break;
case 16:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11100;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16;
break;
case 32:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11101;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32;
break;
case 64:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11110;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64;
break;
case 128:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = 0b11111;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128;
break;
}
/* Set control registers.*/
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.ONCE = 0;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.LENGTH = 0;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.DIR = 0;
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.ONCE = 0U;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.LENGTH = 0U;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.DIR = 0U;
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U;
/* Set secondary source.*/
switch (icup->config->channel) {
case ICU_CHANNEL_1:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00000;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_0_INPUT_PIN;
break;
case ICU_CHANNEL_2:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00001;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_1_INPUT_PIN;
break;
case ICU_CHANNEL_3:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00010;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_2_INPUT_PIN;
break;
case ICU_CHANNEL_4:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00011;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_3_INPUT_PIN;
break;
case ICU_CHANNEL_5:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00100;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_4_INPUT_PIN;
break;
case ICU_CHANNEL_6:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = 0b00101;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_5_INPUT_PIN;
break;
}
/* Set secondary source polarity.*/
if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 0;
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 0U;
}
else {
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 1U;
@ -736,131 +760,135 @@ CH_IRQ_HANDLER(SPC5_ETIMER2_TC5IR_HANDLER) {
* @notapi
*/
void icu_lld_init(void) {
/* Submodules initially all not in use.*/
icu_active_submodules0 = 0;
icu_active_submodules1 = 0;
icu_active_submodules2 = 0;
#if SPC5_ICU_USE_SMOD0
/* Driver initialization.*/
icuObjectInit(&ICUD1);
ICUD1.etimerp = &SPC5_ETIMER_0;
ICUD1.smod_number = 0;
ICUD1.smod_number = 0U;
#endif
#if SPC5_ICU_USE_SMOD1
/* Driver initialization.*/
icuObjectInit(&ICUD2);
ICUD2.etimerp = &SPC5_ETIMER_0;
ICUD2.smod_number = 1;
ICUD2.smod_number = 1U;
#endif
#if SPC5_ICU_USE_SMOD2
/* Driver initialization.*/
icuObjectInit(&ICUD3);
ICUD3.etimerp = &SPC5_ETIMER_0;
ICUD3.smod_number = 2;
ICUD3.smod_number = 2U;
#endif
#if SPC5_ICU_USE_SMOD3
/* Driver initialization.*/
icuObjectInit(&ICUD4);
ICUD4.etimerp = &SPC5_ETIMER_0;
ICUD4.smod_number = 3;
ICUD4.smod_number = 3U;
#endif
#if SPC5_ICU_USE_SMOD4
/* Driver initialization.*/
icuObjectInit(&ICUD5);
ICUD5.etimerp = &SPC5_ETIMER_0;
ICUD5.smod_number = 4;
ICUD5.smod_number = 4U;
#endif
#if SPC5_ICU_USE_SMOD5
/* Driver initialization.*/
icuObjectInit(&ICUD6);
ICUD6.etimerp = &SPC5_ETIMER_0;
ICUD6.smod_number = 5;
ICUD6.smod_number = 5U;
#endif
#if SPC5_ICU_USE_SMOD6
/* Driver initialization.*/
icuObjectInit(&ICUD7);
ICUD7.etimerp = &SPC5_ETIMER_1;
ICUD7.smod_number = 0;
ICUD7.smod_number = 0U;
#endif
#if SPC5_ICU_USE_SMOD7
/* Driver initialization.*/
icuObjectInit(&ICUD8);
ICUD8.etimerp = &SPC5_ETIMER_1;
ICUD8.smod_number = 1;
ICUD8.smod_number = 1U;
#endif
#if SPC5_ICU_USE_SMOD8
/* Driver initialization.*/
icuObjectInit(&ICUD9);
ICUD9.etimerp = &SPC5_ETIMER_1;
ICUD9.smod_number = 2;
ICUD9.smod_number = 2U;
#endif
#if SPC5_ICU_USE_SMOD9
/* Driver initialization.*/
icuObjectInit(&ICUD10);
ICUD10.etimerp = &SPC5_ETIMER_1;
ICUD10.smod_number = 3;
ICUD10.smod_number = 3U;
#endif
#if SPC5_ICU_USE_SMOD10
/* Driver initialization.*/
icuObjectInit(&ICUD11);
ICUD11.etimerp = &SPC5_ETIMER_1;
ICUD11.smod_number = 4;
ICUD11.smod_number = 4U;
#endif
#if SPC5_ICU_USE_SMOD11
/* Driver initialization.*/
icuObjectInit(&ICUD12);
ICUD12.etimerp = &SPC5_ETIMER_1;
ICUD12.smod_number = 5;
ICUD12.smod_number = 5U;
#endif
#if SPC5_ICU_USE_SMOD12
/* Driver initialization.*/
icuObjectInit(&ICUD13);
ICUD13.etimerp = &SPC5_ETIMER_2;
ICUD13.smod_number = 0;
ICUD13.smod_number = 0U;
#endif
#if SPC5_ICU_USE_SMOD13
/* Driver initialization.*/
icuObjectInit(&ICUD14);
ICUD14.etimerp = &SPC5_ETIMER_2;
ICUD14.smod_number = 1;
ICUD14.smod_number = 1U;
#endif
#if SPC5_ICU_USE_SMOD14
/* Driver initialization.*/
icuObjectInit(&ICUD15);
ICUD15.etimerp = &SPC5_ETIMER_2;
ICUD15.smod_number = 2;
ICUD15.smod_number = 2U;
#endif
#if SPC5_ICU_USE_SMOD15
/* Driver initialization.*/
icuObjectInit(&ICUD16);
ICUD16.etimerp = &SPC5_ETIMER_2;
ICUD16.smod_number = 3;
ICUD16.smod_number = 3U;
#endif
#if SPC5_ICU_USE_SMOD16
/* Driver initialization.*/
icuObjectInit(&ICUD17);
ICUD17.etimerp = &SPC5_ETIMER_2;
ICUD17.smod_number = 4;
ICUD17.smod_number = 4U;
#endif
#if SPC5_ICU_USE_SMOD17
/* Driver initialization.*/
icuObjectInit(&ICUD18);
ICUD18.etimerp = &SPC5_ETIMER_2;
ICUD18.smod_number = 5;
ICUD18.smod_number = 5U;
#endif
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || \
@ -924,158 +952,142 @@ void icu_lld_start(ICUDriver *icup) {
(icup->config->channel == ICU_CHANNEL_6),
"icu_lld_start(), #1", "invalid input");
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 || \
SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5
uint8_t SMOD0 = 0;
uint8_t SMOD1 = 0;
uint8_t SMOD2 = 0;
uint8_t SMOD3 = 0;
uint8_t SMOD4 = 0;
uint8_t SMOD5 = 0;
#endif
#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 || \
SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11
uint8_t SMOD6 = 0;
uint8_t SMOD7 = 0;
uint8_t SMOD8 = 0;
uint8_t SMOD9 = 0;
uint8_t SMOD10 = 0;
uint8_t SMOD11 = 0;
#endif
#if SPC5_ICU_USE_SMOD12 || SPC5_ICU_USE_SMOD13 || SPC5_ICU_USE_SMOD14 || \
SPC5_ICU_USE_SMOD15 || SPC5_ICU_USE_SMOD16 || SPC5_ICU_USE_SMOD17
uint8_t SMOD12 = 0;
uint8_t SMOD13 = 0;
uint8_t SMOD14 = 0;
uint8_t SMOD15 = 0;
uint8_t SMOD16 = 0;
uint8_t SMOD17 = 0;
#endif
#if SPC5_ICU_USE_SMOD0
if (ICUD1.state == ICU_READY)
SMOD0 = 1U;
#endif
#if SPC5_ICU_USE_SMOD1
if (ICUD2.state == ICU_READY)
SMOD1 = 1U;
#endif
#if SPC5_ICU_USE_SMOD2
if (ICUD3.state == ICU_READY)
SMOD2 = 1U;
#endif
#if SPC5_ICU_USE_SMOD3
if (ICUD4.state == ICU_READY)
SMOD3 = 1U;
#endif
#if SPC5_ICU_USE_SMOD4
if (ICUD5.state == ICU_READY)
SMOD4 = 1U;
#endif
#if SPC5_ICU_USE_SMOD5
if (ICUD6.state == ICU_READY)
SMOD5 = 1U;
#endif
#if SPC5_ICU_USE_SMOD6
if (ICUD7.state == ICU_READY)
SMOD6 = 1U;
#endif
#if SPC5_ICU_USE_SMOD7
if (ICUD8.state == ICU_READY)
SMOD7 = 1U;
#endif
#if SPC5_ICU_USE_SMOD8
if (ICUD9.state == ICU_READY)
SMOD8 = 1U;
#endif
#if SPC5_ICU_USE_SMOD9
if (ICUD10.state == ICU_READY)
SMOD9 = 1U;
#endif
#if SPC5_ICU_USE_SMOD10
if (ICUD11.state == ICU_READY)
SMOD10 = 1U;
#endif
#if SPC5_ICU_USE_SMOD11
if (ICUD12.state == ICU_READY)
SMOD11 = 1U;
#endif
#if SPC5_ICU_USE_SMOD12
if (ICUD13.state == ICU_READY)
SMOD12 = 1U;
#endif
#if SPC5_ICU_USE_SMOD13
if (ICUD14.state == ICU_READY)
SMOD13 = 1U;
#endif
#if SPC5_ICU_USE_SMOD14
if (ICUD15.state == ICU_READY)
SMOD14 = 1U;
#endif
#if SPC5_ICU_USE_SMOD15
if (ICUD16.state == ICU_READY)
SMOD15 = 1U;
#endif
#if SPC5_ICU_USE_SMOD16
if (ICUD17.state == ICU_READY)
SMOD16 = 1U;
#endif
#if SPC5_ICU_USE_SMOD17
if (ICUD18.state == ICU_READY)
SMOD17 = 1U;
#endif
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 || \
SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5
/* Set Peripheral Clock.*/
if (!(SMOD0 || SMOD1 || SMOD2 || SMOD3 || SMOD4 || SMOD5)) {
halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
SPC5_ICU_ETIMER0_START_PCTL);
}
#endif
#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 || \
SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11
/* Set Peripheral Clock.*/
if (!(SMOD6 || SMOD7 || SMOD8 || SMOD9 || SMOD10 || SMOD11)) {
halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
SPC5_ICU_ETIMER1_START_PCTL);
}
#endif
#if SPC5_ICU_USE_SMOD12 || SPC5_ICU_USE_SMOD13 || SPC5_ICU_USE_SMOD14 || \
SPC5_ICU_USE_SMOD15 || SPC5_ICU_USE_SMOD16 || SPC5_ICU_USE_SMOD17
/* Set Peripheral Clock.*/
if (!(SMOD12 || SMOD13 || SMOD14 || SMOD15 || SMOD16 || SMOD17)) {
halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
SPC5_ICU_ETIMER2_START_PCTL);
}
#endif
chDbgAssert(icu_active_submodules0 < 6, "icu_lld_start(), #1",
"too many submodules");
chDbgAssert(icu_active_submodules1 < 6, "icu_lld_start(), #1",
"too many submodules");
chDbgAssert(icu_active_submodules2 < 6, "icu_lld_start(), #1",
"too many submodules");
if (icup->state == ICU_STOP) {
#if SPC5_ICU_USE_SMOD0
if (&ICUD1 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD1
if (&ICUD2 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD2
if (&ICUD3 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD3
if (&ICUD4 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD4
if (&ICUD5 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD5
if (&ICUD6 == icup)
icu_active_submodules0++;
#endif
#if SPC5_ICU_USE_SMOD6
if (&ICUD7 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD7
if (&ICUD8 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD8
if (&ICUD9 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD9
if (&ICUD10 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD10
if (&ICUD11 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD11
if (&ICUD12 == icup)
icu_active_submodules1++;
#endif
#if SPC5_ICU_USE_SMOD12
if (&ICUD13 == icup)
icu_active_submodules2++;
#endif
#if SPC5_ICU_USE_SMOD13
if (&ICUD14 == icup)
icu_active_submodules2++;
#endif
#if SPC5_ICU_USE_SMOD14
if (&ICUD15 == icup)
icu_active_submodules2++;
#endif
#if SPC5_ICU_USE_SMOD15
if (&ICUD16 == icup)
icu_active_submodules2++;
#endif
#if SPC5_ICU_USE_SMOD16
if (&ICUD17 == icup)
icu_active_submodules2++;
#endif
#if SPC5_ICU_USE_SMOD17
if (&ICUD18 == icup)
icu_active_submodules2++;
#endif
/* Set eTimer0 Clock.*/
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 || \
SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5
/* If this is the first Submodule activated then the eTimer0 is enabled.*/
if (icu_active_submodules0 == 1) {
halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
SPC5_ICU_ETIMER0_START_PCTL);
}
#endif
/* Set eTimer1 Clock.*/
#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 || \
SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11
/* If this is the first Submodule activated then the eTimer1 is enabled.*/
if (icu_active_submodules1 == 1) {
halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
SPC5_ICU_ETIMER1_START_PCTL);
}
#endif
/* Set eTimer2 Clock.*/
#if SPC5_ICU_USE_SMOD12 || SPC5_ICU_USE_SMOD13 || SPC5_ICU_USE_SMOD14 || \
SPC5_ICU_USE_SMOD15 || SPC5_ICU_USE_SMOD16 || SPC5_ICU_USE_SMOD17
/* If this is the first Submodule activated then the eTimer2 is enabled.*/
if (icu_active_submodules2 == 1) {
halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
SPC5_ICU_ETIMER2_START_PCTL);
}
#endif
/* Timer disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = 0b000;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
SPC5_ETIMER_CNTMODE_NO_OPERATION;
/* Clear pending IRQs (if any).*/
icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
/* All IRQs and DMA requests disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0x0000;
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0U;
/* Compare Load 1 disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0b000;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0U;
/* Compare Load 2 disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0b000;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0U;
/* Capture 1 disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = 0b00;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
SPC5_ETIMER_CPT1MODE_DISABLED;
/* Capture 2 disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = 0b00;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
SPC5_ETIMER_CPT2MODE_DISABLED;
/* Counter reset to zero.*/
icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0x0000;
icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0U;
}
/* Configuration.*/
@ -1090,192 +1102,168 @@ void icu_lld_start(ICUDriver *icup) {
* @notapi
*/
void icu_lld_stop(ICUDriver *icup) {
chDbgAssert(icu_active_submodules0 < 6, "icu_lld_stop(), #1",
"too many submodules");
chDbgAssert(icu_active_submodules1 < 6, "icu_lld_stop(), #1",
"too many submodules");
chDbgAssert(icu_active_submodules2 < 6, "icu_lld_stop(), #1",
"too many submodules");
if (icup->state == ICU_READY) {
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 || \
SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5
uint8_t SMOD0 = 0;
uint8_t SMOD1 = 0;
uint8_t SMOD2 = 0;
uint8_t SMOD3 = 0;
uint8_t SMOD4 = 0;
uint8_t SMOD5 = 0;
#endif
#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 || \
SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11
uint8_t SMOD6 = 0;
uint8_t SMOD7 = 0;
uint8_t SMOD8 = 0;
uint8_t SMOD9 = 0;
uint8_t SMOD10 = 0;
uint8_t SMOD11 = 0;
#endif
#if SPC5_ICU_USE_SMOD12 || SPC5_ICU_USE_SMOD13 || SPC5_ICU_USE_SMOD14 || \
SPC5_ICU_USE_SMOD15 || SPC5_ICU_USE_SMOD16 || SPC5_ICU_USE_SMOD17
uint8_t SMOD12 = 0;
uint8_t SMOD13 = 0;
uint8_t SMOD14 = 0;
uint8_t SMOD15 = 0;
uint8_t SMOD16 = 0;
uint8_t SMOD17 = 0;
#endif
#if SPC5_ICU_USE_SMOD0
if (&ICUD1 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111110;
SMOD0 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFE;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD1
if (&ICUD2 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111101;
SMOD1 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFD;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD2
if (&ICUD3 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111011;
SMOD2 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFB;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD3
if (&ICUD4 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11110111;
SMOD3 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xF7;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD4
if (&ICUD5 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11101111;
SMOD4 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xEF;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD5
if (&ICUD6 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11011111;
SMOD5 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xDF;
icu_active_submodules0--;
}
#endif
#if SPC5_ICU_USE_SMOD6
if (&ICUD7 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111110;
SMOD6 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFE;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD7
if (&ICUD8 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111101;
SMOD7 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFD;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD8
if (&ICUD9 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111011;
SMOD8 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFB;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD9
if (&ICUD10 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11110111;
SMOD9 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xF7;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD10
if (&ICUD11 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11101111;
SMOD10 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xEF;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD11
if (&ICUD12 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11011111;
SMOD11 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xDF;
icu_active_submodules1--;
}
#endif
#if SPC5_ICU_USE_SMOD12
if (&ICUD13 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111110;
SMOD12 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFE;
icu_active_submodules2--;
}
#endif
#if SPC5_ICU_USE_SMOD13
if (&ICUD14 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111101;
SMOD13 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFD;
icu_active_submodules2--;
}
#endif
#if SPC5_ICU_USE_SMOD14
if (&ICUD15 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11111011;
SMOD14 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xFB;
icu_active_submodules2--;
}
#endif
#if SPC5_ICU_USE_SMOD15
if (&ICUD16 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11110111;
SMOD5 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xF7;
icu_active_submodules2--;
}
#endif
#if SPC5_ICU_USE_SMOD16
if (&ICUD17 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11101111;
SMOD16 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xEF;
icu_active_submodules2--;
}
#endif
#if SPC5_ICU_USE_SMOD17
if (&ICUD18 == icup) {
/* Disable channel.*/
icup->etimerp->ENBL.B.ENBL &= 0b11011111;
SMOD17 = 1U;
icup->etimerp->ENBL.B.ENBL &= 0xDF;
icu_active_submodules2--;
}
#endif
/* eTimer0 clock deactivation.*/
#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 || \
SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5
if (SMOD0 || SMOD1 || SMOD2 || SMOD3 || SMOD4 || SMOD5) {
/* Clock deactivation.*/
/* If it is the last active submodules then the eTimer0 is disabled.*/
if (icu_active_submodules0 == 0) {
if (icup->etimerp->ENBL.B.ENBL == 0x00) {
halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
SPC5_ICU_ETIMER0_STOP_PCTL);
}
}
#endif
/* eTimer1 clock deactivation.*/
#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 || \
SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11
if (SMOD6 || SMOD7 || SMOD8 || SMOD9 || SMOD10 || SMOD11) {
/* Clock deactivation.*/
/* If it is the last active submodules then the eTimer1 is disabled.*/
if (icu_active_submodules1 == 0) {
if (icup->etimerp->ENBL.B.ENBL == 0x00) {
halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
SPC5_ICU_ETIMER1_STOP_PCTL);
}
}
#endif
/* eTimer2 clock deactivation.*/
#if SPC5_ICU_USE_SMOD12 || SPC5_ICU_USE_SMOD13 || SPC5_ICU_USE_SMOD14 || \
SPC5_ICU_USE_SMOD15 || SPC5_ICU_USE_SMOD16 || SPC5_ICU_USE_SMOD17
if (SMOD12 || SMOD13 || SMOD14 || SMOD15 || SMOD16 || SMOD17) {
/* Clock deactivation.*/
/* If it is the last active submodules then the eTimer2 is disabled.*/
if (icu_active_submodules2 == 0) {
if (icup->etimerp->ENBL.B.ENBL == 0x00) {
halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
SPC5_ICU_ETIMER2_STOP_PCTL);
@ -1298,8 +1286,10 @@ void icu_lld_enable(ICUDriver *icup) {
icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
/* Set Capture 1 and Capture 2 Mode.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = 0b10;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = 0b01;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
SPC5_ETIMER_CPT1MODE_RISING_EDGE;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
SPC5_ETIMER_CPT2MODE_FALLING_EDGE;
/* Active interrupts.*/
if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
@ -1311,14 +1301,16 @@ void icu_lld_enable(ICUDriver *icup) {
}
/* Set Capture FIFO Water Mark.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CFWM = 0b00;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CFWM = 0U;
/* Enable Counter.*/
if (ICU_SKIP_FIRST_CAPTURE) {
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = 0b011;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
SPC5_ETIMER_CNTMODE_RFE_SIHA;
}
else {
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = 0b001;
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
SPC5_ETIMER_CNTMODE_RE;
}
/* Enable Capture process.*/
@ -1335,22 +1327,24 @@ void icu_lld_enable(ICUDriver *icup) {
void icu_lld_disable(ICUDriver *icup) {
/* Disable Capture process.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 0;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 0U;
/* Clear pending IRQs (if any).*/
icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
/* Set Capture 1 and Capture 2 Mode to Disabled.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = 0b00;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = 0b00;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
SPC5_ETIMER_CPT1MODE_DISABLED;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
SPC5_ETIMER_CPT2MODE_DISABLED;
/* Disable interrupts.*/
if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 0;
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 0;
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 0U;
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 0U;
}
if (icup->config->overflow_cb != NULL)
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 0;
icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 0U;
}
#endif /* HAL_USE_ICU */

142
os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
View File

@ -22,6 +22,7 @@
#ifndef _ICU_LLD_H_
#define _ICU_LLD_H_
#include "spc5_etimer.h"
#if HAL_USE_ICU || defined(__DOXYGEN__)
@ -39,9 +40,45 @@
* @note The default is @p FALSE.
*/
#if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__)
#define ICU_SKIP_FIRST_CAPTURE FALSE
#define ICU_SKIP_FIRST_CAPTURE FALSE
#endif
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1 0x18
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2 0x19
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4 0x1A
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8 0x1B
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16 0x1C
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32 0x1D
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64 0x1E
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128 0x1F
#define SPC5_ETIMER_COUNTER_0_INPUT_PIN 0U
#define SPC5_ETIMER_COUNTER_1_INPUT_PIN 1U
#define SPC5_ETIMER_COUNTER_2_INPUT_PIN 2U
#define SPC5_ETIMER_COUNTER_3_INPUT_PIN 3U
#define SPC5_ETIMER_COUNTER_4_INPUT_PIN 4U
#define SPC5_ETIMER_COUNTER_5_INPUT_PIN 5U
#define SPC5_ETIMER_CNTMODE_NO_OPERATION 0U
#define SPC5_ETIMER_CNTMODE_RE 1U
#define SPC5_ETIMER_CNTMODE_RFE 2U
#define SPC5_ETIMER_CNTMODE_RFE_SIHA 3U
#define SPC5_ETIMER_CNTMODE_QUADRATURE 4U
#define SPC5_ETIMER_CNTMODE_RE_SSSD 5U
#define SPC5_ETIMER_CNTMODE_ESS_TRIGGER 6U
#define SPC5_ETIMER_CNTMODE_CASCADE 7U
#define SPC5_ETIMER_CPT1MODE_DISABLED 0U
#define SPC5_ETIMER_CPT1MODE_FALLING_EDGE 1U
#define SPC5_ETIMER_CPT1MODE_RISING_EDGE 2U
#define SPC5_ETIMER_CPT1MODE_ANY_EDGE 3U
#define SPC5_ETIMER_CPT2MODE_DISABLED 0U
#define SPC5_ETIMER_CPT2MODE_FALLING_EDGE 1U
#define SPC5_ETIMER_CPT2MODE_RISING_EDGE 2U
#define SPC5_ETIMER_CPT2MODE_ANY_EDGE 3U
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -57,7 +94,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD0) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD0 TRUE
#define SPC5_ICU_USE_SMOD0 TRUE
#endif
/**
@ -66,7 +103,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD1) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD1 TRUE
#define SPC5_ICU_USE_SMOD1 TRUE
#endif
/**
@ -75,7 +112,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD2) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD2 TRUE
#define SPC5_ICU_USE_SMOD2 TRUE
#endif
/**
@ -84,7 +121,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD3) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD3 TRUE
#define SPC5_ICU_USE_SMOD3 TRUE
#endif
/**
@ -93,7 +130,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD4) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD4 TRUE
#define SPC5_ICU_USE_SMOD4 TRUE
#endif
/**
@ -102,56 +139,56 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD5) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD5 TRUE
#define SPC5_ICU_USE_SMOD5 TRUE
#endif
/**
* @brief eTimer0 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_ETIMER0_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER0_PRIORITY 7
#define SPC5_ICU_ETIMER0_PRIORITY 7
#endif
/**
* @brief ICUD1 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD0_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD0_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD2 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD1_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD1_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD3 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD2_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD2_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD4 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD3_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD3_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD5 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD4_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD4_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD6 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD5_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD5_IRQ_PRIORITY 7
#endif
/**
@ -161,8 +198,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER0_START_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#endif
/**
@ -172,8 +209,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER0_STOP_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#endif
#endif
@ -184,7 +221,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD6) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD6 TRUE
#define SPC5_ICU_USE_SMOD6 TRUE
#endif
/**
@ -193,7 +230,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD7) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD7 TRUE
#define SPC5_ICU_USE_SMOD7 TRUE
#endif
/**
@ -202,7 +239,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD8) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD8 TRUE
#define SPC5_ICU_USE_SMOD8 TRUE
#endif
/**
@ -211,7 +248,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD9) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD9 TRUE
#define SPC5_ICU_USE_SMOD9 TRUE
#endif
/**
@ -220,7 +257,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD10) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD10 TRUE
#define SPC5_ICU_USE_SMOD10 TRUE
#endif
/**
@ -229,56 +266,56 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD11) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD11 TRUE
#define SPC5_ICU_USE_SMOD11 TRUE
#endif
/**
* @brief eTimer1 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_ETIMER1_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER1_PRIORITY 7
#define SPC5_ICU_ETIMER1_PRIORITY 7
#endif
/**
* @brief ICUD7 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD6_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD6_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD6_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD8 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD7_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD7_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD7_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD9 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD8_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD8_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD10 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD9_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD9_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD11 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD10_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD10_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD12 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD11_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD11_IRQ_PRIORITY 7
#endif
/**
@ -288,8 +325,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER1_START_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#endif
/**
@ -299,8 +336,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER1_STOP_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#endif
#endif
@ -311,7 +348,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD12) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD12 TRUE
#define SPC5_ICU_USE_SMOD12 TRUE
#endif
/**
@ -320,7 +357,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD13) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD13 TRUE
#define SPC5_ICU_USE_SMOD13 TRUE
#endif
/**
@ -329,7 +366,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD14) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD14 TRUE
#define SPC5_ICU_USE_SMOD14 TRUE
#endif
/**
@ -338,7 +375,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD15) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD15 TRUE
#define SPC5_ICU_USE_SMOD15 TRUE
#endif
/**
@ -347,7 +384,7 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD16) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD16 TRUE
#define SPC5_ICU_USE_SMOD16 TRUE
#endif
/**
@ -356,56 +393,56 @@
* @note The default is @p TRUE.
*/
#if !defined(SPC5_ICU_USE_SMOD17) || defined(__DOXYGEN__)
#define SPC5_ICU_USE_SMOD17 TRUE
#define SPC5_ICU_USE_SMOD17 TRUE
#endif
/**
* @brief eTimer2 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_ETIMER12_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER2_PRIORITY 7
#define SPC5_ICU_ETIMER2_PRIORITY 7
#endif
/**
* @brief ICUD13 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD12_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD12_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD14 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD13_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD13_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD15 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD14_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD14_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD16 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD15_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD15_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD17 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD16_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD16_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD18 interrupt priority level setting.
*/
#if !defined(SPC5_ICU_SMOD17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_ICU_SMOD17_IRQ_PRIORITY 7
#define SPC5_ICU_SMOD17_IRQ_PRIORITY 7
#endif
/**
@ -415,8 +452,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER2_START_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#endif
/**
@ -426,8 +463,8 @@
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_ICU_ETIMER2_STOP_PCTL) || defined(__DOXYGEN__)
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#endif
#endif
/** @} */
@ -475,7 +512,6 @@
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
#include "etimer.h"
/**
* @brief ICU driver mode.

0
os/hal/platforms/SPC5xx/eTimer_v1/etimer.h → os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h
View File