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ChibiOS
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Custom board.h. Hardware related chages. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4251 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2012-06-01 18:07:01 +00:00
parent 72ecead37c
commit 2f6c0acd6a
1 changed files with 6 additions and 5 deletions
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11
boards/NONSTANDARD_STM32F4_BARTHESS1/board.h
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@ -70,6 +70,7 @@
#define GPIOA_JTDI 15
#define GPIOB_RECEIVER_PPM 0
#define GPIOB_TACHOMETER 1
#define GPIOB_BOOT1 2
#define GPIOB_JTDO 3
#define GPIOB_NJTRST 4
@ -113,7 +114,6 @@
#define GPIOE_PWM5 9
#define GPIOE_ITG3200_INT 10
#define GPIOE_PWM6 11
#define GPIOE_TACHOMETER 12
#define GPIOE_PWM7 13
#define GPIOE_PWM8 14
#define GPIOE_MMA8451_INT2 15
@ -222,6 +222,7 @@
/*
* Port B setup.
#define GPIOB_RECEIVER_PPM 0
#define GPIOB_TACHOMETER 1
#define GPIOB_BOOT1 2
#define GPIOB_JTDO 3
#define GPIOB_NJTRST 4
@ -233,7 +234,7 @@
*/
/* 0x00000280 */
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_RECEIVER_PPM) | \
PIN_MODE_INPUT(1) | \
PIN_MODE_INPUT(GPIOB_TACHOMETER) | \
PIN_MODE_INPUT(GPIOB_BOOT1) | \
PIN_MODE_ALTERNATE(GPIOB_JTDO) | \
PIN_MODE_ALTERNATE(GPIOB_NJTRST) | \
@ -258,7 +259,7 @@
#define VAL_GPIOB_OSPEEDR 0x000000C0//0xAAAAAAEA
/* 0x00000100 */
#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLDOWN(GPIOB_RECEIVER_PPM) | \
PIN_PUDR_PULLUP(1) | \
PIN_PUDR_PULLDOWN(GPIOB_TACHOMETER) | \
PIN_PUDR_FLOATING(GPIOB_BOOT1) | \
PIN_PUDR_FLOATING(GPIOB_JTDO) | \
PIN_PUDR_PULLUP(GPIOB_NJTRST) | \
@ -424,7 +425,7 @@
PIN_MODE_ALTERNATE(GPIOE_PWM5) | \
PIN_MODE_INPUT(GPIOE_ITG3200_INT) | \
PIN_MODE_ALTERNATE(GPIOE_PWM6) | \
PIN_MODE_INPUT(GPIOE_TACHOMETER) | \
PIN_MODE_INPUT(12) | \
PIN_MODE_ALTERNATE(GPIOE_PWM7) | \
PIN_MODE_ALTERNATE(GPIOE_PWM8) | \
PIN_MODE_INPUT(GPIOE_MMA8451_INT2))
@ -452,7 +453,7 @@
PIN_PUDR_PULLDOWN(GPIOE_PWM5) | \
PIN_PUDR_PULLDOWN(GPIOE_ITG3200_INT) | \
PIN_PUDR_PULLDOWN(GPIOE_PWM6) | \
PIN_PUDR_PULLUP(GPIOE_TACHOMETER) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLDOWN(GPIOE_PWM7) | \
PIN_PUDR_PULLDOWN(GPIOE_PWM8) | \
PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT2))