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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14822 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2021-09-23 14:57:22 +00:00
parent 06e40c102d
commit 301e1a68a4
3 changed files with 80 additions and 4 deletions
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28
os/hal/ports/STM32/STM32MP1xx/hal_lld.c
View File

@ -46,6 +46,17 @@ uint32_t SystemCoreClock = 0; //STM32_HCLK;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* Static PWR configurations.*/
PWR->MCUCR = STM32_PWR_MCUCR;
PWR->MCUWKUPENR = STM32_PWR_MCUWKUPENR;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@ -91,6 +102,23 @@ void stm32_clock_init(void) {
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Trying to allocate SYSCFG.*/
rccEnableAPB3(RCC_MC_APB3ENSETR_SYSCFGEN, false);
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Clocks setup.*/
// lse_init();
#if !STM32_TZEN_ENABLED
lsi_init();
#endif
#if !STM32_TZEN_ENABLED && !STM32_MCKPROT_ENABLED
hsi_init();
csi_init();
hse_init();
#endif
#endif /* STM32_NO_INIT */
}
#endif /* !defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */

8
os/hal/ports/STM32/STM32MP1xx/hal_lld.h
View File

@ -160,14 +160,14 @@
* @brief If enabled assumes TZEN active.
*/
#if !defined(STM32_TZEN_ENABLED) || defined(__DOXYGEN__)
#define STM32_TZEN_ENABLED TRUE
#define STM32_TZEN_ENABLED FALSE
#endif
/**
* @brief If enabled assumes MCKPROT active.
*/
#if !defined(STM32_MCKPROT_ENABLED) || defined(__DOXYGEN__)
#define STM32_MCKPROT_ENABLED TRUE
#define STM32_MCKPROT_ENABLED FALSE
#endif
/**
@ -181,14 +181,14 @@
* @brief PWR MCUCR register initialization value.
*/
#if !defined(STM32_PWR_MCUCR) || defined(__DOXYGEN__)
#define STM32_PWR_MCUCR 2222222222
#define STM32_PWR_MCUCR 0
#endif
/**
* @brief PWR MCUWKUPENR register initialization value.
*/
#if !defined(STM32_PWR_MCUWKUPENR) || defined(__DOXYGEN__)
#define STM32_PWR_MCUWKUPENR 2222222222
#define STM32_PWR_MCUWKUPENR 0
#endif
/**

48
os/hal/ports/STM32/STM32MP1xx/stm32_rcc.h
View File

@ -98,6 +98,54 @@ __STATIC_FORCEINLINE void rccResetAPB1(uint32_t mask) {
(void) RCC->APB1RSTCLRR;
}
/**
* @brief Enables the clock of one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
__STATIC_FORCEINLINE void rccEnableAPB3(uint32_t mask, bool lp) {
RCC->MC_APB3ENSETR = mask;
if (lp) {
RCC->MC_APB3LPENSETR = mask;
}
else {
RCC->MC_APB3LPENCLRR = mask;
}
(void) RCC->MC_APB3ENSETR;
}
/**
* @brief Disables the clock of one or more peripheral on the APB3 bus).
*
* @param[in] mask APB3 peripherals mask
*
* @api
*/
__STATIC_FORCEINLINE void rccDisableAPB3(uint32_t mask) {
RCC->MC_APB3ENCLRR = mask;
RCC->MC_APB3LPENCLRR = mask;
(void) RCC->MC_APB3LPENCLRR;
}
/**
* @brief Resets one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
*
* @api
*/
__STATIC_FORCEINLINE void rccResetAPB3(uint32_t mask) {
RCC->APB3RSTSETR = mask;
RCC->APB3RSTCLRR = mask;
(void) RCC->APB3RSTCLRR;
}
/**
* @brief Enables the clock of one or more peripheral on the AHB4 bus.
*