I2C. All polling waitins code replaced by "waiting" GPT interrups. Documentation fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3167 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -22,7 +22,12 @@
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* @defgroup I2C I2C Driver
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* @defgroup I2C I2C Driver
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* @brief Generic I2C Driver.
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* @brief Generic I2C Driver.
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* @details This module implements a generic I2C (Inter-Integrated Circuit)
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* @details This module implements a generic I2C (Inter-Integrated Circuit)
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* driver.
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* driver. On STM32 platform you can choose method of waiting START
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* and STOP bits: polling wait or wait using GPT. GPT method use
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* one timer per I2C interface, on the other hand -- polling is
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* block function that starts transfer.
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* @note If you decide to use polling wait -- do NOT start transmit or
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* receive from callback because it run in ISR context.
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* @pre In order to use the I2C driver the @p HAL_USE_I2C option
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* @pre In order to use the I2C driver the @p HAL_USE_I2C option
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* must be enabled in @p halconf.h.
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* must be enabled in @p halconf.h.
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*
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*
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@ -34,20 +39,23 @@
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* @dot
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* @dot
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digraph example {
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digraph example {
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rankdir="LR";
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rankdir="LR";
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node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
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node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="false",
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width="0.9", height="0.9"];
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width="0.9", height="0.9"];
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edge [fontname=Helvetica, fontsize=8];
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edge [fontname=Helvetica, fontsize=8];
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uninit [label="I2C_UNINIT", style="bold"];
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uninit [label="I2C_UNINIT", style="bold"];
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stop [label="I2C_STOP\nLow Power"];
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stop [label="I2C_STOP\nLow Power"];
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ready [label="I2C_READY\nClock Enabled"];
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ready [label="I2C_READY\nClock Enabled"];
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active [label="I2C_ACTIVE\nBus Active"];
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active_tx [label="I2C_ACTIVE_TRANSMIT\nBus TX Active"];
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active_rx [label="I2C_ACTIVE_RECEIVE\nBus RX Active"];
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uninit -> stop [label="i2cInit()"];
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uninit -> stop [label="i2cInit()"];
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stop -> stop [label="i2cStop()"];
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stop -> stop [label="i2cStop()"];
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stop -> ready [label="i2cStart()"];
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stop -> ready [label="i2cStart()"];
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ready -> active [label="i2cMasterTransmit()\ni2cMasterReceive()"];
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ready -> active_tx [label="i2cMasterTransmit()"];
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active -> ready [label="_i2c_isr_code()"];
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ready -> active_rx [label="i2cMasterReceive()"];
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active_tx -> ready [label="_i2c_isr_code()"];
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active_rx -> ready [label="_i2c_isr_code()"];
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ready -> stop [label="i2cStop()"];
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ready -> stop [label="i2cStop()"];
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}
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}
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* @enddot
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* @enddot
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@ -82,8 +82,9 @@ typedef enum {
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I2C_UNINIT = 0, /**< @brief Not initialized. */
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I2C_UNINIT = 0, /**< @brief Not initialized. */
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I2C_STOP = 1, /**< @brief Stopped. */
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I2C_STOP = 1, /**< @brief Stopped. */
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I2C_READY = 2, /**< @brief Ready. */
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I2C_READY = 2, /**< @brief Ready. */
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I2C_ACTIVE_TRANSMIT = 3,/**< @brief Transmit in progress. */
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I2C_ACTIVE_TRANSMIT = 3, /**< @brief Transmit in progress. */
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I2C_ACTIVE_RECEIVE = 4, /**< @brief Receive in progress. */
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I2C_ACTIVE_RECEIVE = 4, /**< @brief Receive in progress. */
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I2C_ACTIVE_TRANSCEIVE = 5, /**< @brief Receive after transmit in progress. */
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/* Slave part. Not realized. */
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/* Slave part. Not realized. */
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I2C_SACTIVE = 10,
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I2C_SACTIVE = 10,
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@ -63,12 +63,10 @@ static volatile uint16_t dbgCR2 = 0;
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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#if STM32_I2C_USE_POLLING_WAIT
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#if STM32_I2C_I2C1_USE_POLLING_WAIT
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#else
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#else
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/*
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/* I2C1 GPT callback. */
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* GPT1 callback.
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static void i2c1gptcb(GPTDriver *gptp) {
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*/
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static void gpt1cb(GPTDriver *gptp) {
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(void)gptp;
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(void)gptp;
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I2CDriver *i2cp = &I2CD1;
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I2CDriver *i2cp = &I2CD1;
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@ -84,18 +82,26 @@ static void gpt1cb(GPTDriver *gptp) {
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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break;
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break;
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case I2C_ACTIVE_TRANSCEIVE:
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i2c_lld_master_transceive(i2cp);
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break;
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default:
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default:
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break;
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break;
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}
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}
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chSysUnlockFromIsr();
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chSysUnlockFromIsr();
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}
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}
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/* I2C1 GPT configuration. */
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static const GPTConfig i2c1gptcfg = {
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1000000, /* 1MHz timer clock.*/
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i2c1gptcb /* Timer callback.*/
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};
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#endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */
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#if STM32_I2C_I2C2_USE_POLLING_WAIT
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#else
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/*
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/* I2C2 GPT callback. */
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* GPT2 callback.
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static void i2c2gptcb(GPTDriver *gptp) {
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*/
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static void gpt2cb(GPTDriver *gptp) {
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(void)gptp;
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(void)gptp;
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I2CDriver *i2cp = &I2CD2;
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I2CDriver *i2cp = &I2CD2;
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@ -111,24 +117,21 @@ static void gpt2cb(GPTDriver *gptp) {
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes);
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break;
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break;
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case I2C_ACTIVE_TRANSCEIVE:
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i2c_lld_master_transceive(i2cp);
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break;
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default:
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default:
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break;
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break;
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}
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}
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chSysUnlockFromIsr();
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chSysUnlockFromIsr();
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}
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}
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/* I2C2 GPT configuration. */
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/* GPT1 configuration. */
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static const GPTConfig i2c2gptcfg = {
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static const GPTConfig gpt1cfg = {
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1000000, /* 1MHz timer clock.*/
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1000000, /* 1MHz timer clock.*/
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gpt1cb /* Timer callback.*/
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i2c2gptcb /* Timer callback.*/
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};
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};
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#endif /* STM32_I2C_I2C2_USE_POLLING_WAIT */
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/* GPT2 configuration. */
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static const GPTConfig gpt2cfg = {
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1000000, /* 1MHz timer clock.*/
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gpt2cb /* Timer callback.*/
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};
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#endif /* STM32_I2C_USE_POLLING_WAIT */
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/**
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/**
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* @brief Function for I2C debugging purpose.
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* @brief Function for I2C debugging purpose.
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@ -322,6 +325,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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}
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}
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else{ /* start reading operation */
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else{ /* start reading operation */
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i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */
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i2c_lld_master_transceive(i2cp);
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i2c_lld_master_transceive(i2cp);
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}
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}
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break;
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break;
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@ -471,12 +475,12 @@ void i2c_lld_init(void) {
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i2cObjectInit(&I2CD1);
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i2cObjectInit(&I2CD1);
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I2CD1.id_i2c = I2C1;
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I2CD1.id_i2c = I2C1;
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#if !(STM32_I2C_I2C1_USE_POLLING_WAIT)
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#if STM32_I2C_I2C1_USE_POLLING_WAIT
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I2CD1.timer = &GPTD1;//TODO: remove hardcode
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I2CD1.timer_cfg = &gpt1cfg;//TODO: remove hardcode
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#else
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I2CD1.timer = NULL;
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I2CD1.timer = NULL;
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I2CD1.timer_cfg = NULL;
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I2CD1.timer_cfg = NULL;
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#else
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I2CD1.timer = &(STM32_I2C_I2C1_USE_GPT_TIM);
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I2CD1.timer_cfg = &i2c1gptcfg;
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#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */
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#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */
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#endif /* STM32_I2C_USE_I2C */
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#endif /* STM32_I2C_USE_I2C */
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@ -487,12 +491,12 @@ void i2c_lld_init(void) {
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i2cObjectInit(&I2CD2);
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i2cObjectInit(&I2CD2);
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I2CD2.id_i2c = I2C2;
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I2CD2.id_i2c = I2C2;
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#if !(STM32_I2C_I2C2_USE_POLLING_WAIT)
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#if STM32_I2C_I2C2_USE_POLLING_WAIT
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I2CD2.timer = &GPTD2;//TODO: remove hardcode
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I2CD2.timer_cfg = &gpt2cfg;//TODO: remove hardcode
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#else
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I2CD2.timer = NULL;
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I2CD2.timer = NULL;
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I2CD2.timer_cfg = NULL;
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I2CD2.timer_cfg = NULL;
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#else
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I2CD2.timer = &(STM32_I2C_I2C2_USE_GPT_TIM);
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I2CD2.timer_cfg = &i2c2gptcfg;
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#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */
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#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */
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#endif /* STM32_I2C_USE_I2C2 */
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#endif /* STM32_I2C_USE_I2C2 */
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@ -700,21 +704,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
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void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr,
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void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr,
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uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) {
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uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) {
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i2cp->slave_addr = slave_addr;
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/* "waiting" for STOP bit routine*/
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i2cp->txbytes = txbytes;
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i2cp->rxbytes = rxbytes;
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i2cp->txbuf = txbuf;
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i2cp->rxbuf = rxbuf;
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if(slave_addr & 0x8000){ /* 10-bit mode used */
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i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */
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i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */
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i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */
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}
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else{
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i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */
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}
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chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED),
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chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED),
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"i2c_lld_master_transmit(), #1", "time to STOP is out");
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"i2c_lld_master_transmit(), #1", "time to STOP is out");
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if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){
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if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){
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@ -727,6 +717,24 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr,
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;
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;
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}
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}
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/* init driver fields */
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i2cp->slave_addr = slave_addr;
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i2cp->txbytes = txbytes;
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i2cp->rxbytes = rxbytes;
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i2cp->txbuf = txbuf;
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i2cp->rxbuf = rxbuf;
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/* init address fields */
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if(slave_addr & 0x8000){ /* 10-bit mode used */
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i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */
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i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */
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i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */
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}
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else{
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i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */
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}
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/* setting flags and register bits */
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i2cp->flags = 0;
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i2cp->flags = 0;
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i2cp->errors = 0;
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i2cp->errors = 0;
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i2cp->id_i2c->CR1 &= ~I2C_CR1_POS;
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i2cp->id_i2c->CR1 &= ~I2C_CR1_POS;
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@ -753,21 +761,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
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"i2c_lld_master_receive(), #1",
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"i2c_lld_master_receive(), #1",
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"some interrupt sources not clear");
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"some interrupt sources not clear");
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i2cp->slave_addr = slave_addr;
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/* "waiting" for STOP bit routine*/
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i2cp->rxbytes = rxbytes;
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i2cp->rxbuf = rxbuf;
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if(slave_addr & 0x8000){ /* 10-bit mode used */
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i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */
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i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */
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i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */
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}
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else{
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i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */
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}
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chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED),
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chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED),
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"i2c_lld_master_receive(), #1", "time to STOP is out");
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"i2c_lld_master_receive(), #1", "time to STOP is out");
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if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){
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if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){
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@ -780,7 +774,22 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
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;
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;
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}
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}
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/* init driver fields */
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i2cp->slave_addr = slave_addr;
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i2cp->rxbytes = rxbytes;
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i2cp->rxbuf = rxbuf;
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/* init address fields */
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if(slave_addr & 0x8000){ /* 10-bit mode used */
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i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */
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i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */
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i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */
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}
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else{
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i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */
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}
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/* setting flags and register bits */
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i2cp->flags |= I2C_FLG_MASTER_RECEIVER;
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i2cp->flags |= I2C_FLG_MASTER_RECEIVER;
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i2cp->errors = 0;
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i2cp->errors = 0;
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@ -814,6 +823,22 @@ void i2c_lld_master_transceive(I2CDriver *i2cp){
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"i2c_lld_master_transceive(), #1",
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"i2c_lld_master_transceive(), #1",
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"");
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"");
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i2cp->id_state = I2C_ACTIVE_TRANSCEIVE;
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/* "waiting" for START bit routine*/
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chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED),
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"i2c_lld_master_transceive(), #1", "time to START is out");
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||||||
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if ((i2cp->id_i2c->CR1 & I2C_CR1_START) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){
|
||||||
|
gptStartOneShot(i2cp->timer, I2C_START_GPT_TIMEOUT);
|
||||||
|
i2cp->flags |= I2C_FLG_TIMER_ARMED;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
while(i2cp->id_i2c->CR1 & I2C_CR1_START)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* init address fields */
|
||||||
if(i2cp->slave_addr & 0x8000){ /* 10-bit mode used */
|
if(i2cp->slave_addr & 0x8000){ /* 10-bit mode used */
|
||||||
i2cp->slave_addr1 = ((i2cp->slave_addr >>7) & 0x0006);/* add the two msb of 10-bit address to the header */
|
i2cp->slave_addr1 = ((i2cp->slave_addr >>7) & 0x0006);/* add the two msb of 10-bit address to the header */
|
||||||
i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */
|
i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */
|
||||||
|
@ -823,9 +848,7 @@ void i2c_lld_master_transceive(I2CDriver *i2cp){
|
||||||
i2cp->slave_addr1 |= 0x01;
|
i2cp->slave_addr1 |= 0x01;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* setting flags and register bits */
|
||||||
|
|
||||||
|
|
||||||
i2cp->flags |= I2C_FLG_MASTER_RECEIVER;
|
i2cp->flags |= I2C_FLG_MASTER_RECEIVER;
|
||||||
i2cp->errors = 0;
|
i2cp->errors = 0;
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */
|
i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */
|
||||||
|
@ -839,17 +862,6 @@ void i2c_lld_master_transceive(I2CDriver *i2cp){
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */
|
i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
//TODO: use timer here also!!
|
|
||||||
|
|
||||||
i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */
|
|
||||||
|
|
||||||
uint32_t timeout = I2C_START_TIMEOUT;
|
|
||||||
while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout--)
|
|
||||||
;
|
|
||||||
chDbgAssert(timeout <= I2C_START_TIMEOUT,
|
|
||||||
"i2c_lld_master_receive(), #1", "time is out");
|
|
||||||
|
|
||||||
i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */
|
i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -20,45 +20,25 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief TODO!!!!!!!!
|
* @brief I2C1 driver synchronization choice between GPT and polling.
|
||||||
* @details If set to @p TRUE than waiting of STOP generation will use
|
* @note The default is polling wait.
|
||||||
* while() loop polling. Otherwise -- virtual timer will be used.
|
|
||||||
* @note The default is @p TRUE.
|
|
||||||
* @note Virtual timer resolution is 1/@p CH_FREQUENCY seconds.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_I2C_I2C1_USE_GPT_TIM1) || \
|
#if !defined(STM32_I2C_I2C1_USE_GPT_TIM) || \
|
||||||
!defined(STM32_I2C_I2C1_USE_GPT_TIM2) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_GPT_TIM3) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_GPT_TIM4) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_GPT_TIM5) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_GPT_TIM8) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_VIRTUAL_TIMER) || \
|
|
||||||
!defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \
|
!defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \
|
||||||
defined(__DOXYGEN__)
|
defined(__DOXYGEN__)
|
||||||
#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE
|
#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C2 driver synchronization choice between GPT and polling.
|
||||||
#if !defined(STM32_I2C_I2C2_USE_GPT_TIM1) || \
|
* @note The default is polling wait.
|
||||||
!defined(STM32_I2C_I2C2_USE_GPT_TIM2) || \
|
*/
|
||||||
!defined(STM32_I2C_I2C2_USE_GPT_TIM3) || \
|
#if !defined(STM32_I2C_I2C2_USE_GPT_TIM) || \
|
||||||
!defined(STM32_I2C_I2C2_USE_GPT_TIM4) || \
|
|
||||||
!defined(STM32_I2C_I2C2_USE_GPT_TIM5) || \
|
|
||||||
!defined(STM32_I2C_I2C2_USE_GPT_TIM8) || \
|
|
||||||
!defined(STM32_I2C_I2C2_USE_VIRTUAL_TIMER) || \
|
|
||||||
!defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \
|
!defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \
|
||||||
defined(__DOXYGEN__)
|
defined(__DOXYGEN__)
|
||||||
#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE
|
#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief I2C1 driver enable switch.
|
* @brief I2C1 driver enable switch.
|
||||||
* @details If set to @p TRUE the support for I2C1 is included.
|
* @details If set to @p TRUE the support for I2C1 is included.
|
||||||
|
@ -127,6 +107,7 @@
|
||||||
#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER)
|
#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
|
#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
|
#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver data structures and types. */
|
/* Driver data structures and types. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
Loading…
Reference in New Issue