andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

the fat lady started singing 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16384 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-09-03 07:42:35 +00:00
parent 0ca6e7b6e9
commit 304755712b
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
os/hal/ports/STM32/STM32H5xx/hal_lld.c
View File

@ -766,6 +766,7 @@ void stm32_clock_init(void) {
/* Switching to the configured SYSCLK source if it is different from HSI.*/
#if STM32_SW != STM32_SW_HSI
RCC->CFGR1 |= STM32_SW; /* Switches on the selected clock source. */
// while(1);
while ((RCC->CFGR1 & STM32_SWS_MASK) != (STM32_SW << 3)) {
/* Wait until SYSCLK is stable.*/
}

10
os/hal/ports/STM32/STM32H5xx/hal_lld.h
View File

@ -103,11 +103,11 @@
* @name VOS field definitions
* @{
*/
#define STM32_VOS_MASK (3U << 14) /**< Core voltage mask. */
#define STM32_VOS_RANGE3 (0U << 14) /**< Core voltage 1 Volt. */
#define STM32_VOS_RANGE2 (1U << 14) /**< Core voltage 1.1 Volts. */
#define STM32_VOS_RANGE1 (2U << 14) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_RANGE0 (3U << 14) /**< Core voltage 1.35 Volts. */
#define STM32_VOS_MASK (3U << 4) /**< Core voltage mask. */
#define STM32_VOS_RANGE3 (0U << 4) /**< Core voltage 1 Volt. */
#define STM32_VOS_RANGE2 (1U << 4) /**< Core voltage 1.1 Volts. */
#define STM32_VOS_RANGE1 (2U << 4) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_RANGE0 (3U << 4) /**< Core voltage 1.35 Volts. */
/** @} */
/**