From 30522d3ac030eac230655ff7de55461f61194694 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 24 Jul 2014 07:37:17 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7065
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/rt/ports/e200/chcore.h | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/os/rt/ports/e200/chcore.h b/os/rt/ports/e200/chcore.h
index 70c936928..cae498eef 100644
--- a/os/rt/ports/e200/chcore.h
+++ b/os/rt/ports/e200/chcore.h
@@ -29,6 +29,8 @@
 #ifndef _CHCORE_H_
 #define _CHCORE_H_
 
+#include "intc.h"
+
 /*===========================================================================*/
 /* Module constants.                                                         */
 /*===========================================================================*/
@@ -410,6 +412,7 @@ extern "C" {
  */
 static inline void port_init(void) {
   uint32_t n;
+  unsigned i;
 
   /* Initializing the SPRG0 register to zero, it is required for interrupts
      handling.*/
@@ -425,8 +428,13 @@ static inline void port_init(void) {
                 "mtIVOR10    %%r3" : : : "r3", "memory");
 #endif
 
-  /* Interrupt controller initialization.*/
-  intc_init();
+  /* INTC initialization, software vector mode, 4 bytes vectors, starting
+     at priority 0.*/
+  INTC_BCR = 0;
+  for (i = 0; i < PPC_CORE_NUMBER; i++) {
+    INTC_CPR(i)   = 0;
+    INTC_IACKR(i) = (uint32_t)_vectors;
+  }
 }
 
 /**