git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6479 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -195,6 +195,7 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
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#if !defined(SPC5_ADC0_WD_HANDLER)
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#error "SPC5_ADC0_WD_HANDLER not defined"
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#endif
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/**
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* @brief ADC0 Watch Dog interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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@ -207,8 +208,9 @@ OSAL_IRQ_HANDLER(SPC5_ADC0_WD_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADCD1.adc_tagp->WTISR.R;
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isr = ADCD1.adc_tagp->WTISR.R;
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ADCD1.adc_tagp->WTISR.R = isr;
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adc_lld_serve_interrupt(&ADCD1, isr);
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OSAL_IRQ_EPILOGUE();
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@ -233,7 +235,7 @@ OSAL_IRQ_HANDLER(SPC5_ADC1_WD_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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isr = ADCD2.adc_tagp->WTISR.R;
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ADCD2.adc_tagp->WTISR.R = isr;
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adc_lld_serve_interrupt(&ADCD2, isr);
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OSAL_IRQ_EPILOGUE();
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@ -302,7 +304,7 @@ void adc_lld_start(ADCDriver *adcp) {
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#endif /* SPC5_ADC_USE_ADC1 */
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osalDbgAssert((adcp->adc_dma_channel != EDMA_ERROR),
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"adc_lld_start(), #1", "DMA channel cannot be allocated");
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"adc_lld_start(), #1", "DMA channel cannot be allocated");
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/* Configures the peripheral.*/
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@ -325,7 +327,11 @@ void adc_lld_start(ADCDriver *adcp) {
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/* Sets ADC Normal Mode.*/
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adcp->adc_tagp->MCR.B.PWDN = 0;
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/* Power up delay.*/
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/* TODO: add a delay of 5uS.*/
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/* Sets analog clock.*/
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/* TODO: make it a static option, move in adc_lld_init().*/
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if (adcp->config->clock == HALF_PERIPHERAL_SET_CLOCK_FREQUENCY) {
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adcp->adc_tagp->MCR.B.ADCLKSEL = 0;
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} else if (adcp->config->clock == PERIPHERAL_SET_CLOCK_FREQUENCY) {
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@ -353,6 +359,8 @@ void adc_lld_stop(ADCDriver *adcp) {
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edmaChannelRelease(adcp->adc_dma_channel);
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/* Clears thresholds’ values and deactives watchdog threshold interrupts.*/
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/* TODO: make the number of WD registers a parameter in the registry, modify
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the configuration structure.*/
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if (adcp->grpp->wtimr != 0) {
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adcp->adc_tagp->TRC[0].R = 0;
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adcp->adc_tagp->TRC[1].R = 0;
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@ -402,12 +410,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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//osalDbgAssert(adcp->grpp->num_channels*2 >= adcp->depth,
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// "adc_lld_start_conversion(), #1", "too many elements");
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/* Active DMA.*/
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adcp->adc_tagp->DMAE.R = ADC_DMAE_DMAEN;
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/* Setting up DMA TCD parameters.*/
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edmaChannelSetup(adcp->adc_dma_channel, /* channel. */
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adcp->adc_tagp->CDR[adcp->grpp->init_channel].B.CDATA, /* src. */
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((uint8_t *)adcp->adc_tagp->CDR[adcp->grpp->init_channel].R) + 2, /* src. */
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adcp->samples, /* dst. */
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4, /* soff, advance by four. */
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2, /* doff, advance by two. */
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@ -423,6 +428,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END |
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((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0)); /* mode. */
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/* Active DMA.*/
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adcp->adc_tagp->DMAE.R = ADC_DMAE_DMAEN;
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/* TODO: make the number of WD registers a parameter in the registry, modify
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the configuration structure.*/
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/* Sets thresholds’ values and active watchdog threshold interrupts if any.*/
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if (adcp->grpp->wtimr != 0) {
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adcp->adc_tagp->TRC[0].R = adcp->grpp->trcr[0];
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@ -436,6 +446,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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adcp->adc_tagp->WTIMR.R = adcp->grpp->wtimr;
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}
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/* mask = ((1 << nchannels) - 1) << firstchannel.*/
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/* TODO: Make the channels a mash in the configuration and just assign it.*/
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/* Active ADC channels for the conversion and sets the ADC DMA channels.*/
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for (i = adcp->grpp->init_channel; i <= adcp->grpp->final_channel; i++) {
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adcp->adc_tagp->NCMR[0].R |= 1U << i;
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