diff --git a/docs/reports/LPC1114-48-GCC.txt b/docs/reports/LPC1114-48-GCC.txt
index 32ea4154e..e5f0a3f3b 100644
--- a/docs/reports/LPC1114-48-GCC.txt
+++ b/docs/reports/LPC1114-48-GCC.txt
@@ -98,51 +98,51 @@ Settings: CLK=48, (2 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.1 (Benchmark, messages #1)
---- Score : 126834 msgs/S, 253668 ctxswc/S
+--- Score : 126786 msgs/S, 253572 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.2 (Benchmark, messages #2)
---- Score : 100879 msgs/S, 201758 ctxswc/S
+--- Score : 100841 msgs/S, 201682 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.3 (Benchmark, messages #3)
---- Score : 100879 msgs/S, 201758 ctxswc/S
+--- Score : 100841 msgs/S, 201682 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.4 (Benchmark, context switch)
---- Score : 380632 ctxswc/S
+--- Score : 380488 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 78390 threads/S
+--- Score : 78359 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 110433 threads/S
+--- Score : 110391 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 31050 reschedules/S, 186300 ctxswc/S
+--- Score : 31038 reschedules/S, 186228 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 253332 ctxswc/S
+--- Score : 253236 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 296368 bytes/S
+--- Score : 296256 bytes/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 350378 timers/S
+--- Score : 350246 timers/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 592280 wait+signal/S
+--- Score : 592052 wait+signal/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 335036 lock+unlock/S
+--- Score : 334912 lock+unlock/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.13 (Benchmark, RAM footprint)
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c
index 5004b2256..f132697d5 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.c
@@ -127,6 +127,33 @@ void port_switch(Thread *ntp, Thread *otp) {
   POP_CONTEXT(r13);
 }
 
+/**
+ * @brief   IRQ epilogue code.
+ *
+ * @param[in] lr        value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+  if (lr != (regarm_t)0xFFFFFFF1) {
+    port_lock_from_isr();
+    if (chSchIsRescRequiredExI()) {
+      register struct extctx *ctxp;
+
+      /* Adding an artificial exception return context, there is no need to
+         populate it fully.*/
+      asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
+      ctxp--;
+      asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
+      ctxp->pc = _port_switch_from_isr;
+      ctxp->xpsr = (regarm_t)0x01000000;
+      /* Note, returning without unlocking is intentional, this is done in
+        order to keep the rest of the context switching atomic.*/
+      return;
+    }
+    port_unlock_from_isr();
+  }
+}
+
 /**
  * @brief   Start a thread by invoking its work function.
  * @details If the work function returns @p chThdExit() is automatically
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
index 4e156f4c4..4cfd7de8a 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.h
@@ -113,26 +113,7 @@ struct intctx {
  * @details This macro must be inserted at the end of all IRQ handlers
  *          enabled to invoke system APIs.
  */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  if (_saved_lr != (regarm_t)0xFFFFFFF1) {                                  \
-    port_lock_from_isr();                                                   \
-    if (chSchIsRescRequiredExI()) {                                         \
-      register struct extctx *ctxp;                                         \
-                                                                            \
-      /* Adding an artificial exception return context, there is no need to \
-         populate it fully.*/                                               \
-      asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");          \
-      ctxp--;                                                               \
-      asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");           \
-      ctxp->pc = _port_switch_from_isr;                                     \
-      ctxp->xpsr = (regarm_t)0x01000000;                                    \
-      /* Note, returning without unlocking is intentional, this is done in  \
-        order to keep the rest of the context switching atomic.*/           \
-      return;                                                               \
-    }                                                                       \
-    port_unlock_from_isr();                                                 \
-  }                                                                         \
-}
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
 
 /**
  * @brief   IRQ handler function declaration.
@@ -223,6 +204,7 @@ extern "C" {
 #endif
   void port_halt(void);
   void port_switch(Thread *ntp, Thread *otp);
+  void _port_irq_epilogue(regarm_t lr);
   void _port_switch_from_isr(void);
   void _port_thread_start(void);
 #ifdef __cplusplus
diff --git a/readme.txt b/readme.txt
index d5526d2f6..5b0f0865a 100644
--- a/readme.txt
+++ b/readme.txt
@@ -86,7 +86,9 @@
 - FIX: Fixed wrong serial driver macros (bug 3173336)(backported to 2.2.1).
 - NEW: Inproved preemption implementation for the Cortex-M0, now it uses
   the NMI vector in order to restore the original context. The change makes
-  IRQ handling faster and also saves some RAM/ROM space (backported to 2.2.3).
+  IRQ handling faster and also saves some RAM/ROM space. The GCC port code
+  now does not inline the epilogue code in each ISR saving significan ROM
+  space for each interrupt handler in the system (backported to 2.2.3).
 - NEW: Added "IRQ STORM" long duration tests for the STM32 and LPC11xx. The
   test demonstrates the system stability in a thread-intensive, progressively
   CPU-saturating, IRQ-intensive long duration test.