diff --git a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
index 1f16178db..3d66dbba6 100644
--- a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
index 4c73f14cc..09eab7e18 100644
--- a/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                4
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                4
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
index 23028e14e..d0d1d5f14 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
@@ -682,7 +682,7 @@
  * @note    The allowed values are 8..127.
  */
 #if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #endif
 
 /**
@@ -732,7 +732,7 @@
  * @note    The allowed values are 8..127.
  */
 #if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #endif
 
 /**
diff --git a/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index 60ef6f35c..c21d9e681 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index b72d64c84..0e0865f98 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
index 7224d710d..90ecf9f0d 100644
--- a/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h b/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
index e221acb67..a5f8ac05e 100644
--- a/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
+++ b/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
@@ -91,13 +91,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                4
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                4
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h b/testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
index e221acb67..a5f8ac05e 100644
--- a/testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
+++ b/testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
@@ -91,13 +91,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                4
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                4
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
index f9f59b3ad..5ea63b0ed 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
index 037151a2b..0b8ea0690 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
@@ -91,13 +91,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                4
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                4
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index 5af31cd7f..78ae5574c 100644
--- a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
index 4ce45752a..bde4310d3 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                1
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                1
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
index e4f0c3119..9922f85a6 100644
--- a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
+++ b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
@@ -93,13 +93,13 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1M_VALUE                4
-#define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1N_VALUE                60
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
 #define STM32_PLLSAI2M_VALUE                4
-#define STM32_PLLSAI2N_VALUE                72
+#define STM32_PLLSAI2N_VALUE                60
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
 #define STM32_PLLSAI2Q_VALUE                6
diff --git a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
index cc9743247..4c53b2fd4 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
@@ -102,13 +102,13 @@
 #define STM32_MCOPRE                        ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
 #define STM32_LSCOSEL                       ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
 #define STM32_PLLSAI1M_VALUE                ${doc.STM32_PLLSAI1M_VALUE!"1"}
-#define STM32_PLLSAI1N_VALUE                ${doc.STM32_PLLSAI1N_VALUE!"72"}
+#define STM32_PLLSAI1N_VALUE                ${doc.STM32_PLLSAI1N_VALUE!"60"}
 #define STM32_PLLSAI1PDIV_VALUE             ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
 #define STM32_PLLSAI1P_VALUE                ${doc.STM32_PLLSAI1P_VALUE!"7"}
 #define STM32_PLLSAI1Q_VALUE                ${doc.STM32_PLLSAI1Q_VALUE!"6"}
 #define STM32_PLLSAI1R_VALUE                ${doc.STM32_PLLSAI1R_VALUE!"6"}
 #define STM32_PLLSAI2M_VALUE                ${doc.STM32_PLLSAI2M_VALUE!"1"}
-#define STM32_PLLSAI2N_VALUE                ${doc.STM32_PLLSAI2N_VALUE!"72"}
+#define STM32_PLLSAI2N_VALUE                ${doc.STM32_PLLSAI2N_VALUE!"60"}
 #define STM32_PLLSAI2PDIV_VALUE             ${doc.STM32_PLLSAI2PDIV_VALUE!"6"}
 #define STM32_PLLSAI2P_VALUE                ${doc.STM32_PLLSAI2P_VALUE!"7"}
 #define STM32_PLLSAI2Q_VALUE                ${doc.STM32_PLLSAI2Q_VALUE!"6"}