From 330701b8d83ac7f70a1e6103d94e2817fea417c0 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 17 Sep 2021 09:32:05 +0000 Subject: [PATCH] MP1-related support files git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14779 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32MP1xx/platform.mk | 34 +++ os/hal/ports/STM32/STM32MP1xx/stm32_dmamux.h | 195 ++++++++++++++++ .../ports/STM32/STM32MP1xx/stm32_registry.h | 219 ++++++++++++++++++ 3 files changed, 448 insertions(+) create mode 100644 os/hal/ports/STM32/STM32MP1xx/platform.mk create mode 100644 os/hal/ports/STM32/STM32MP1xx/stm32_dmamux.h create mode 100644 os/hal/ports/STM32/STM32MP1xx/stm32_registry.h diff --git a/os/hal/ports/STM32/STM32MP1xx/platform.mk b/os/hal/ports/STM32/STM32MP1xx/platform.mk new file mode 100644 index 000000000..edb8f222d --- /dev/null +++ b/os/hal/ports/STM32/STM32MP1xx/platform.mk @@ -0,0 +1,34 @@ +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32MP1xx/stm32_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32MP1xx/hal_lld.c + +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS)/os/hal/ports/STM32/STM32MP1xx + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/STM32/STM32MP1xx/stm32_dmamux.h b/os/hal/ports/STM32/STM32MP1xx/stm32_dmamux.h new file mode 100644 index 000000000..391b4bf4d --- /dev/null +++ b/os/hal/ports/STM32/STM32MP1xx/stm32_dmamux.h @@ -0,0 +1,195 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32MP1xx/stm32_dmamux.h + * @brief STM32MP1xx DMAMUX handler header. + * + * @addtogroup STM32MP1xx_DMAMUX + * @{ + */ + +#ifndef STM32_DMAMUX_H +#define STM32_DMAMUX_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name DMAMUX1 request sources + * @{ + */ +#define STM32_DMAMUX1_REQ_GEN0 1 +#define STM32_DMAMUX1_REQ_GEN1 2 +#define STM32_DMAMUX1_REQ_GEN2 3 +#define STM32_DMAMUX1_REQ_GEN3 4 +#define STM32_DMAMUX1_REQ_GEN4 5 +#define STM32_DMAMUX1_REQ_GEN5 6 +#define STM32_DMAMUX1_REQ_GEN6 7 +#define STM32_DMAMUX1_REQ_GEN7 8 +#define STM32_DMAMUX1_ADC1 9 +#define STM32_DMAMUX1_ADC2 10 +#define STM32_DMAMUX1_TIM1_CH1 11 +#define STM32_DMAMUX1_TIM1_CH2 12 +#define STM32_DMAMUX1_TIM1_CH3 13 +#define STM32_DMAMUX1_TIM1_CH4 14 +#define STM32_DMAMUX1_TIM1_UP 15 +#define STM32_DMAMUX1_TIM1_TRIG 16 +#define STM32_DMAMUX1_TIM1_COM 17 +#define STM32_DMAMUX1_TIM2_CH1 18 +#define STM32_DMAMUX1_TIM2_CH2 19 +#define STM32_DMAMUX1_TIM2_CH3 20 +#define STM32_DMAMUX1_TIM2_CH4 21 +#define STM32_DMAMUX1_TIM2_UP 22 +#define STM32_DMAMUX1_TIM3_CH1 23 +#define STM32_DMAMUX1_TIM3_CH2 24 +#define STM32_DMAMUX1_TIM3_CH3 25 +#define STM32_DMAMUX1_TIM3_CH4 26 +#define STM32_DMAMUX1_TIM3_UP 27 +#define STM32_DMAMUX1_TIM3_TRIG 28 +#define STM32_DMAMUX1_TIM4_CH1 29 +#define STM32_DMAMUX1_TIM4_CH2 30 +#define STM32_DMAMUX1_TIM4_CH3 31 +#define STM32_DMAMUX1_TIM4_UP 32 +#define STM32_DMAMUX1_I2C1_RX 33 +#define STM32_DMAMUX1_I2C1_TX 34 +#define STM32_DMAMUX1_I2C2_RX 35 +#define STM32_DMAMUX1_I2C2_TX 36 +#define STM32_DMAMUX1_SPI1_RX 37 +#define STM32_DMAMUX1_SPI1_TX 38 +#define STM32_DMAMUX1_SPI2_RX 39 +#define STM32_DMAMUX1_SPI2_TX 40 +#define STM32_DMAMUX1_RSVD41 41 +#define STM32_DMAMUX1_RSVD42 42 +#define STM32_DMAMUX1_USART2_RX 43 +#define STM32_DMAMUX1_USART2_TX 44 +#define STM32_DMAMUX1_USART3_RX 45 +#define STM32_DMAMUX1_USART3_TX 46 +#define STM32_DMAMUX1_TIM8_CH1 47 +#define STM32_DMAMUX1_TIM8_CH2 48 +#define STM32_DMAMUX1_TIM8_CH3 49 +#define STM32_DMAMUX1_TIM8_CH4 50 +#define STM32_DMAMUX1_TIM8_UP 51 +#define STM32_DMAMUX1_TIM8_TRIG 52 +#define STM32_DMAMUX1_TIM8_COM 53 +#define STM32_DMAMUX1_RSVD54 54 +#define STM32_DMAMUX1_TIM5_CH1 55 +#define STM32_DMAMUX1_TIM5_CH2 56 +#define STM32_DMAMUX1_TIM5_CH3 57 +#define STM32_DMAMUX1_TIM5_CH4 58 +#define STM32_DMAMUX1_TIM5_UP 59 +#define STM32_DMAMUX1_TIM5_TRIG 60 +#define STM32_DMAMUX1_SPI3_RX 61 +#define STM32_DMAMUX1_SPI3_TX 62 +#define STM32_DMAMUX1_UART4_RX 63 +#define STM32_DMAMUX1_UART4_TX 64 +#define STM32_DMAMUX1_UART5_RX 65 +#define STM32_DMAMUX1_UART5_TX 66 +#define STM32_DMAMUX1_DAC1_CH1 67 +#define STM32_DMAMUX1_DAC1_CH2 68 +#define STM32_DMAMUX1_TIM6_UP 69 +#define STM32_DMAMUX1_TIM7_UP 70 +#define STM32_DMAMUX1_USART6_RX 71 +#define STM32_DMAMUX1_USART6_TX 72 +#define STM32_DMAMUX1_I2C3_RX 73 +#define STM32_DMAMUX1_I2C3_TX 74 +#define STM32_DMAMUX1_DCMI 75 +#define STM32_DMAMUX1_CRYP2_IN 76 +#define STM32_DMAMUX1_CRYP2_OUT 77 +#define STM32_DMAMUX1_HASH2_IN 78 +#define STM32_DMAMUX1_UART7_RX 79 +#define STM32_DMAMUX1_UART7_TX 80 +#define STM32_DMAMUX1_UART8_RX 81 +#define STM32_DMAMUX1_UART8_TX 82 +#define STM32_DMAMUX1_SPI4_RX 83 +#define STM32_DMAMUX1_SPI4_TX 84 +#define STM32_DMAMUX1_SPI5_RX 85 +#define STM32_DMAMUX1_SPI5_TX 86 +#define STM32_DMAMUX1_SAI1_A 87 +#define STM32_DMAMUX1_SAI1_B 88 +#define STM32_DMAMUX1_SAI2_A 89 +#define STM32_DMAMUX1_SAI2_B 90 +#define STM32_DMAMUX1_DFSDM1_FLT4 91 +#define STM32_DMAMUX1_DFSDM1_FLT5 92 +#define STM32_DMAMUX1_SPDIFRX_DT 93 +#define STM32_DMAMUX1_SPDIFRX_CS 94 +#define STM32_DMAMUX1_RSVD95 95 +#define STM32_DMAMUX1_RSVD96 96 +#define STM32_DMAMUX1_RSVD97 97 +#define STM32_DMAMUX1_RSVD98 98 +#define STM32_DMAMUX1_SAI4_A 99 +#define STM32_DMAMUX1_SAI4_B 100 +#define STM32_DMAMUX1_DFSDM1_FLT0 101 +#define STM32_DMAMUX1_DFSDM1_FLT1 102 +#define STM32_DMAMUX1_DFSDM1_FLT2 103 +#define STM32_DMAMUX1_DFSDM1_FLT3 104 +#define STM32_DMAMUX1_TIM15_CH1 105 +#define STM32_DMAMUX1_TIM15_UP 106 +#define STM32_DMAMUX1_TIM15_TRIG 107 +#define STM32_DMAMUX1_TIM15_COM 108 +#define STM32_DMAMUX1_TIM16_CH1 109 +#define STM32_DMAMUX1_TIM16_UP 110 +#define STM32_DMAMUX1_TIM17_CH1 111 +#define STM32_DMAMUX1_TIM17_UP 112 +#define STM32_DMAMUX1_SAI3_A 113 +#define STM32_DMAMUX1_SAI3_B 114 +#define STM32_DMAMUX1_I2C5_RX 115 +#define STM32_DMAMUX1_I2C5_TX 116 +#define STM32_DMAMUX1_RSVD117 117 +#define STM32_DMAMUX1_RSVD118 118 +#define STM32_DMAMUX1_RSVD119 119 +#define STM32_DMAMUX1_RSVD120 120 +#define STM32_DMAMUX1_RSVD121 121 +#define STM32_DMAMUX1_RSVD122 122 +#define STM32_DMAMUX1_RSVD123 123 +#define STM32_DMAMUX1_RSVD124 124 +#define STM32_DMAMUX1_RSVD125 125 +#define STM32_DMAMUX1_RSVD126 126 +#define STM32_DMAMUX1_RSVD127 127 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_DMAMUX_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h new file mode 100644 index 000000000..6a73e823b --- /dev/null +++ b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h @@ -0,0 +1,219 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32MP1xx/stm32_registry.h + * @brief STM32MP1xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32MP1xx capabilities + * @{ + */ + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* STM32MP157Axx, STM32MP157Cxx, STM32MP157Dxx, STM32MP157Fxx. */ +/* STM32MP153Axx, STM32MP153Cxx, STM32MP153Dxx, STM32MP153Fxx. */ +/* STM32MP151Axx, STM32MP151Cxx, STM32MP151Dxx, STM32MP151Fxx. */ +/*===========================================================================*/ + +#if defined(STM32MP157Axx) || defined(STM32MP157Cxx) || \ + defined(STM32MP157Dxx) || defined(STM32MP157Fxx) || \ + defined(STM32MP153Axx) || defined(STM32MP153Cxx) || \ + defined(STM32MP153Dxx) || defined(STM32MP153Fxx) || \ + defined(STM32MP151Axx) || defined(STM32MP151Cxx) || \ + defined(STM32MP151Dxx) || defined(STM32MP151Fxx) || \ + defined(__DOXYGEN__) + +/* ADC attributes.*/ + +/* CAN attributes.*/ + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE +#define STM32_HAS_DAC3_CH1 FALSE +#define STM32_HAS_DAC3_CH2 FALSE +#define STM32_HAS_DAC4_CH1 FALSE +#define STM32_HAS_DAC4_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE +#define STM32_DMA1_NUM_CHANNELS 8 +#define STM32_DMA2_NUM_CHANNELS 8 + +/* ETH attributes.*/ + +/* EXTI attributes.*/ + +/* Flash attributes.*/ + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOJ TRUE +#define STM32_HAS_GPIOK TRUE +#define STM32_HAS_GPIOZ TRUE +#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \ + RCC_AHB4ENR_GPIOBEN | \ + RCC_AHB4ENR_GPIOCEN | \ + RCC_AHB4ENR_GPIODEN | \ + RCC_AHB4ENR_GPIOEEN | \ + RCC_AHB4ENR_GPIOFEN | \ + RCC_AHB4ENR_GPIOGEN | \ + RCC_AHB4ENR_GPIOHEN | \ + RCC_AHB4ENR_GPIOIEN | \ + RCC_AHB4ENR_GPIOJEN | \ + RCC_AHB4ENR_GPIOKEN) + +/* I2C attributes.*/ + +/* OCTOSPI attributes.*/ + +/* SDMMC attributes.*/ + +/* SPI attributes.*/ + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM20 TRUE +#define STM32_TIM20_IS_32BITS FALSE +#define STM32_TIM20_CHANNELS 6 + +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 FALSE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_USART6 TRUE +#define STM32_HAS_UART7 TRUE +#define STM32_HAS_UART8 TRUE + +/* OTG/USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +#endif /* defined(STM32MP157Axx) || defined(STM32MP157Cxx) || + defined(STM32MP157Dxx) || defined(STM32MP157Fxx) || + defined(STM32MP153Axx) || defined(STM32MP153Cxx) || + defined(STM32MP153Dxx) || defined(STM32MP153Fxx) || + defined(STM32MP151Axx) || defined(STM32MP151Cxx) || + defined(STM32MP151Dxx) || defined(STM32MP151Fxx) */ + +/** @} */ + +#endif /* STM32_REGISTRY_H */ + +/** @} */