andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3645 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-12-21 18:49:04 +00:00
parent 6100dc08a6
commit 334c7d645d
50 changed files with 306 additions and 841 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
os/hal/platforms/LPC11xx/gpt_lld.c
View File

@ -209,25 +209,25 @@ void gpt_lld_start(GPTDriver *gptp) {
#if LPC11xx_GPT_USE_CT16B0 #if LPC11xx_GPT_USE_CT16B0
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
NVICEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
#if LPC11xx_GPT_USE_CT16B1 #if LPC11xx_GPT_USE_CT16B1
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
NVICEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
} }
#endif #endif
#if LPC11xx_GPT_USE_CT32B0 #if LPC11xx_GPT_USE_CT32B0
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
NVICEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
#if LPC11xx_GPT_USE_CT32B1 #if LPC11xx_GPT_USE_CT32B1
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
NVICEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
} }
@ -259,25 +259,25 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if LPC11xx_GPT_USE_CT16B0 #if LPC11xx_GPT_USE_CT16B0
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
NVICDisableVector(TIMER_16_0_IRQn); nvicDisableVector(TIMER_16_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
} }
#endif #endif
#if LPC11xx_GPT_USE_CT16B1 #if LPC11xx_GPT_USE_CT16B1
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
NVICDisableVector(TIMER_16_1_IRQn); nvicDisableVector(TIMER_16_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
} }
#endif #endif
#if LPC11xx_GPT_USE_CT32B0 #if LPC11xx_GPT_USE_CT32B0
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
NVICDisableVector(TIMER_32_0_IRQn); nvicDisableVector(TIMER_32_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
} }
#endif #endif
#if LPC11xx_GPT_USE_CT32B1 #if LPC11xx_GPT_USE_CT32B1
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
NVICDisableVector(TIMER_32_1_IRQn); nvicDisableVector(TIMER_32_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
} }
#endif #endif

2
os/hal/platforms/LPC11xx/hal_lld.c
View File

@ -62,7 +62,7 @@
void hal_lld_init(void) { void hal_lld_init(void) {
/* SysTick initialization using the system clock.*/ /* SysTick initialization using the system clock.*/
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1; SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1;
SysTick->VAL = 0; SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

4
os/hal/platforms/LPC11xx/serial_lld.c
View File

@ -265,7 +265,7 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (&SD1 == sdp) { if (&SD1 == sdp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
LPC_SYSCON->UARTCLKDIV = LPC11xx_SERIAL_UART0CLKDIV; LPC_SYSCON->UARTCLKDIV = LPC11xx_SERIAL_UART0CLKDIV;
NVICEnableVector(UART_IRQn, nvicEnableVector(UART_IRQn,
CORTEX_PRIORITY_MASK(LPC11xx_SERIAL_UART0_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(LPC11xx_SERIAL_UART0_IRQ_PRIORITY));
} }
#endif #endif
@ -290,7 +290,7 @@ void sd_lld_stop(SerialDriver *sdp) {
if (&SD1 == sdp) { if (&SD1 == sdp) {
LPC_SYSCON->UARTCLKDIV = 0; LPC_SYSCON->UARTCLKDIV = 0;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
NVICDisableVector(UART_IRQn); nvicDisableVector(UART_IRQn);
return; return;
} }
#endif #endif

8
os/hal/platforms/LPC11xx/spi_lld.c
View File

@ -215,7 +215,7 @@ void spi_lld_start(SPIDriver *spip) {
LPC_SYSCON->SSP0CLKDIV = LPC11xx_SPI_SSP0CLKDIV; LPC_SYSCON->SSP0CLKDIV = LPC11xx_SPI_SSP0CLKDIV;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
LPC_SYSCON->PRESETCTRL |= 1; LPC_SYSCON->PRESETCTRL |= 1;
NVICEnableVector(SSP0_IRQn, nvicEnableVector(SSP0_IRQn,
CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP0_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP0_IRQ_PRIORITY));
} }
#endif #endif
@ -224,7 +224,7 @@ void spi_lld_start(SPIDriver *spip) {
LPC_SYSCON->SSP1CLKDIV = LPC11xx_SPI_SSP1CLKDIV; LPC_SYSCON->SSP1CLKDIV = LPC11xx_SPI_SSP1CLKDIV;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18);
LPC_SYSCON->PRESETCTRL |= 4; LPC_SYSCON->PRESETCTRL |= 4;
NVICEnableVector(SSP1_IRQn, nvicEnableVector(SSP1_IRQn,
CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP1_IRQ_PRIORITY));
} }
#endif #endif
@ -255,7 +255,7 @@ void spi_lld_stop(SPIDriver *spip) {
LPC_SYSCON->PRESETCTRL &= ~1; LPC_SYSCON->PRESETCTRL &= ~1;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
LPC_SYSCON->SSP0CLKDIV = 0; LPC_SYSCON->SSP0CLKDIV = 0;
NVICDisableVector(SSP0_IRQn); nvicDisableVector(SSP0_IRQn);
} }
#endif #endif
#if LPC11xx_SPI_USE_SSP1 #if LPC11xx_SPI_USE_SSP1
@ -263,7 +263,7 @@ void spi_lld_stop(SPIDriver *spip) {
LPC_SYSCON->PRESETCTRL &= ~4; LPC_SYSCON->PRESETCTRL &= ~4;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18);
LPC_SYSCON->SSP1CLKDIV = 0; LPC_SYSCON->SSP1CLKDIV = 0;
NVICDisableVector(SSP1_IRQn); nvicDisableVector(SSP1_IRQn);
} }
#endif #endif
} }

16
os/hal/platforms/LPC13xx/gpt_lld.c
View File

@ -209,25 +209,25 @@ void gpt_lld_start(GPTDriver *gptp) {
#if LPC13xx_GPT_USE_CT16B0 #if LPC13xx_GPT_USE_CT16B0
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
NVICEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
#if LPC13xx_GPT_USE_CT16B1 #if LPC13xx_GPT_USE_CT16B1
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
NVICEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
} }
#endif #endif
#if LPC13xx_GPT_USE_CT32B0 #if LPC13xx_GPT_USE_CT32B0
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
NVICEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
#if LPC13xx_GPT_USE_CT32B1 #if LPC13xx_GPT_USE_CT32B1
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
NVICEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
} }
#endif #endif
} }
@ -259,25 +259,25 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if LPC13xx_GPT_USE_CT16B0 #if LPC13xx_GPT_USE_CT16B0
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
NVICDisableVector(TIMER_16_0_IRQn); nvicDisableVector(TIMER_16_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
} }
#endif #endif
#if LPC13xx_GPT_USE_CT16B1 #if LPC13xx_GPT_USE_CT16B1
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
NVICDisableVector(TIMER_16_1_IRQn); nvicDisableVector(TIMER_16_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
} }
#endif #endif
#if LPC13xx_GPT_USE_CT32B0 #if LPC13xx_GPT_USE_CT32B0
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
NVICDisableVector(TIMER_32_0_IRQn); nvicDisableVector(TIMER_32_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
} }
#endif #endif
#if LPC13xx_GPT_USE_CT32B1 #if LPC13xx_GPT_USE_CT32B1
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
NVICDisableVector(TIMER_32_1_IRQn); nvicDisableVector(TIMER_32_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
} }
#endif #endif

2
os/hal/platforms/LPC13xx/hal_lld.c
View File

@ -62,7 +62,7 @@
void hal_lld_init(void) { void hal_lld_init(void) {
/* SysTick initialization using the system clock.*/ /* SysTick initialization using the system clock.*/
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1; SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1;
SysTick->VAL = 0; SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

4
os/hal/platforms/LPC13xx/serial_lld.c
View File

@ -265,7 +265,7 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (&SD1 == sdp) { if (&SD1 == sdp) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
LPC_SYSCON->UARTCLKDIV = LPC13xx_SERIAL_UART0CLKDIV; LPC_SYSCON->UARTCLKDIV = LPC13xx_SERIAL_UART0CLKDIV;
NVICEnableVector(UART_IRQn, nvicEnableVector(UART_IRQn,
CORTEX_PRIORITY_MASK(LPC13xx_SERIAL_UART0_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(LPC13xx_SERIAL_UART0_IRQ_PRIORITY));
} }
#endif #endif
@ -290,7 +290,7 @@ void sd_lld_stop(SerialDriver *sdp) {
if (&SD1 == sdp) { if (&SD1 == sdp) {
LPC_SYSCON->UARTCLKDIV = 0; LPC_SYSCON->UARTCLKDIV = 0;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
NVICDisableVector(UART_IRQn); nvicDisableVector(UART_IRQn);
return; return;
} }
#endif #endif

4
os/hal/platforms/LPC13xx/spi_lld.c
View File

@ -186,7 +186,7 @@ void spi_lld_start(SPIDriver *spip) {
LPC_SYSCON->SSPCLKDIV = LPC13xx_SPI_SSP0CLKDIV; LPC_SYSCON->SSPCLKDIV = LPC13xx_SPI_SSP0CLKDIV;
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
LPC_SYSCON->PRESETCTRL |= 1; LPC_SYSCON->PRESETCTRL |= 1;
NVICEnableVector(SSP_IRQn, nvicEnableVector(SSP_IRQn,
CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP0_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP0_IRQ_PRIORITY));
} }
#endif #endif
@ -217,7 +217,7 @@ void spi_lld_stop(SPIDriver *spip) {
LPC_SYSCON->PRESETCTRL &= ~1; LPC_SYSCON->PRESETCTRL &= ~1;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
LPC_SYSCON->SSPCLKDIV = 0; LPC_SYSCON->SSPCLKDIV = 0;
NVICDisableVector(SSP_IRQn); nvicDisableVector(SSP_IRQn);
} }
#endif #endif
} }

16
os/hal/platforms/STM32/I2Cv1/i2c_lld.c
View File

@ -534,10 +534,10 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C1 #if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
#if I2C_SUPPORTS_CALLBACKS #if I2C_SUPPORTS_CALLBACKS
NVICEnableVector(I2C1_EV_IRQn, nvicEnableVector(I2C1_EV_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* I2C_SUPPORTS_CALLBACKS */
NVICEnableVector(I2C1_ER_IRQn, nvicEnableVector(I2C1_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
rccEnableI2C1(FALSE); rccEnableI2C1(FALSE);
} }
@ -545,10 +545,10 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) { if (&I2CD2 == i2cp) {
#if I2C_SUPPORTS_CALLBACKS #if I2C_SUPPORTS_CALLBACKS
NVICEnableVector(I2C2_EV_IRQn, nvicEnableVector(I2C2_EV_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* I2C_SUPPORTS_CALLBACKS */
NVICEnableVector(I2C2_ER_IRQn, nvicEnableVector(I2C2_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
rccEnableI2C2(FALSE); rccEnableI2C2(FALSE);
} }
@ -698,15 +698,15 @@ void i2c_lld_stop(I2CDriver *i2cp) {
if (i2cp->id_state == I2C_READY) { /* If in ready state then disables the I2C clock.*/ if (i2cp->id_state == I2C_READY) { /* If in ready state then disables the I2C clock.*/
#if STM32_I2C_USE_I2C1 #if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
NVICDisableVector(I2C1_EV_IRQn); nvicDisableVector(I2C1_EV_IRQn);
NVICDisableVector(I2C1_ER_IRQn); nvicDisableVector(I2C1_ER_IRQn);
rccDisableI2C1(FALSE); rccDisableI2C1(FALSE);
} }
#endif #endif
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) { if (&I2CD2 == i2cp) {
NVICDisableVector(I2C2_EV_IRQn); nvicDisableVector(I2C2_EV_IRQn);
NVICDisableVector(I2C2_ER_IRQn); nvicDisableVector(I2C2_ER_IRQn);
rccDisableI2C2(FALSE); rccDisableI2C2(FALSE);
} }
#endif #endif

4
os/hal/platforms/STM32/RTCv1/rtc_lld.c
View File

@ -316,11 +316,11 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
rtc_lld_wait_write(); rtc_lld_wait_write();
RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
rtc_lld_wait_write(); rtc_lld_wait_write();
NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));
RTC->CRH |= RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; RTC->CRH |= RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
} }
else { else {
NVICDisableVector(RTC_IRQn); nvicDisableVector(RTC_IRQn);
rtc_lld_wait_write(); rtc_lld_wait_write();
RTC->CRL = 0; RTC->CRL = 0;
RTC->CRH = 0; RTC->CRH = 0;

8
os/hal/platforms/STM32/USBv1/usb_lld.c
View File

@ -287,9 +287,9 @@ void usb_lld_start(USBDriver *usbp) {
STM32_USB->CNTR = CNTR_FRES; STM32_USB->CNTR = CNTR_FRES;
/* Enabling the USB IRQ vectors, this also gives enough time to allow /* Enabling the USB IRQ vectors, this also gives enough time to allow
the transceiver power up (1uS).*/ the transceiver power up (1uS).*/
NVICEnableVector(19, nvicEnableVector(19,
CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY));
NVICEnableVector(20, nvicEnableVector(20,
CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY));
/* Releases the USB reset.*/ /* Releases the USB reset.*/
STM32_USB->CNTR = 0; STM32_USB->CNTR = 0;
@ -314,8 +314,8 @@ void usb_lld_stop(USBDriver *usbp) {
if (usbp->state == USB_STOP) { if (usbp->state == USB_STOP) {
#if STM32_USB_USE_USB1 #if STM32_USB_USE_USB1
if (&USBD1 == usbp) { if (&USBD1 == usbp) {
NVICDisableVector(19); nvicDisableVector(19);
NVICDisableVector(20); nvicDisableVector(20);
STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
rccDisableUSB(FALSE); rccDisableUSB(FALSE);
} }

16
os/hal/platforms/STM32/can_lld.c
View File

@ -184,13 +184,13 @@ void can_lld_start(CANDriver *canp) {
/* Clock activation.*/ /* Clock activation.*/
#if STM32_CAN_USE_CAN1 #if STM32_CAN_USE_CAN1
if (&CAND1 == canp) { if (&CAND1 == canp) {
NVICEnableVector(USB_HP_CAN1_TX_IRQn, nvicEnableVector(USB_HP_CAN1_TX_IRQn,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
NVICEnableVector(USB_LP_CAN1_RX0_IRQn, nvicEnableVector(USB_LP_CAN1_RX0_IRQn,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
NVICEnableVector(CAN1_RX1_IRQn, nvicEnableVector(CAN1_RX1_IRQn,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
NVICEnableVector(CAN1_SCE_IRQn, nvicEnableVector(CAN1_SCE_IRQn,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
rccEnableCAN1(FALSE); rccEnableCAN1(FALSE);
} }
@ -272,10 +272,10 @@ void can_lld_stop(CANDriver *canp) {
if (&CAND1 == canp) { if (&CAND1 == canp) {
CAN1->MCR = 0x00010002; /* Register reset value. */ CAN1->MCR = 0x00010002; /* Register reset value. */
CAN1->IER = 0x00000000; /* All sources disabled. */ CAN1->IER = 0x00000000; /* All sources disabled. */
NVICDisableVector(USB_HP_CAN1_TX_IRQn); nvicDisableVector(USB_HP_CAN1_TX_IRQn);
NVICDisableVector(USB_LP_CAN1_RX0_IRQn); nvicDisableVector(USB_LP_CAN1_RX0_IRQn);
NVICDisableVector(CAN1_RX1_IRQn); nvicDisableVector(CAN1_RX1_IRQn);
NVICDisableVector(CAN1_SCE_IRQn); nvicDisableVector(CAN1_SCE_IRQn);
rccDisableCAN1(FALSE); rccDisableCAN1(FALSE);
} }
#endif #endif

84
os/hal/platforms/STM32/ext_lld.c
View File

@ -434,55 +434,55 @@ void ext_lld_start(EXTDriver *extp) {
if (extp->state == EXT_STOP) { if (extp->state == EXT_STOP) {
/* Clock activation.*/ /* Clock activation.*/
NVICEnableVector(EXTI0_IRQn, nvicEnableVector(EXTI0_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
NVICEnableVector(EXTI1_IRQn, nvicEnableVector(EXTI1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
NVICEnableVector(EXTI2_IRQn, nvicEnableVector(EXTI2_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
NVICEnableVector(EXTI3_IRQn, nvicEnableVector(EXTI3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
NVICEnableVector(EXTI4_IRQn, nvicEnableVector(EXTI4_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
NVICEnableVector(EXTI9_5_IRQn, nvicEnableVector(EXTI9_5_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
NVICEnableVector(EXTI15_10_IRQn, nvicEnableVector(EXTI15_10_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
NVICEnableVector(PVD_IRQn, nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
NVICEnableVector(RTC_Alarm_IRQn, nvicEnableVector(RTC_Alarm_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
#if defined(STM32L1XX_MD) #if defined(STM32L1XX_MD)
/* EXTI vectors specific to STM32L1xx.*/ /* EXTI vectors specific to STM32L1xx.*/
NVICEnableVector(USB_FS_WKUP_IRQn, nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
NVICEnableVector(TAMPER_STAMP_IRQn, nvicEnableVector(TAMPER_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
NVICEnableVector(RTC_WKUP_IRQn, nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
NVICEnableVector(COMP_IRQn, nvicEnableVector(COMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
#elif defined(STM32F2XX) || defined(STM32F4XX) #elif defined(STM32F2XX) || defined(STM32F4XX)
/* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/
NVICEnableVector(OTG_FS_WKUP_IRQn, nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
NVICEnableVector(ETH_WKUP_IRQn, nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
NVICEnableVector(OTG_HS_WKUP_IRQn, nvicEnableVector(OTG_HS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
NVICEnableVector(TAMP_STAMP_IRQn, nvicEnableVector(TAMP_STAMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
NVICEnableVector(RTC_WKUP_IRQn, nvicEnableVector(RTC_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
#elif defined(STM32F10X_CL) #elif defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/ /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
NVICEnableVector(OTG_FS_WKUP_IRQn, nvicEnableVector(OTG_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
NVICEnableVector(ETH_WKUP_IRQn, nvicEnableVector(ETH_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
#else #else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
NVICEnableVector(USB_FS_WKUP_IRQn, nvicEnableVector(USB_FS_WKUP_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
#endif #endif
} }
@ -529,35 +529,35 @@ void ext_lld_start(EXTDriver *extp) {
void ext_lld_stop(EXTDriver *extp) { void ext_lld_stop(EXTDriver *extp) {
if (extp->state == EXT_ACTIVE) { if (extp->state == EXT_ACTIVE) {
NVICDisableVector(EXTI0_IRQn); nvicDisableVector(EXTI0_IRQn);
NVICDisableVector(EXTI1_IRQn); nvicDisableVector(EXTI1_IRQn);
NVICDisableVector(EXTI2_IRQn); nvicDisableVector(EXTI2_IRQn);
NVICDisableVector(EXTI3_IRQn); nvicDisableVector(EXTI3_IRQn);
NVICDisableVector(EXTI4_IRQn); nvicDisableVector(EXTI4_IRQn);
NVICDisableVector(EXTI9_5_IRQn); nvicDisableVector(EXTI9_5_IRQn);
NVICDisableVector(EXTI15_10_IRQn); nvicDisableVector(EXTI15_10_IRQn);
NVICDisableVector(PVD_IRQn); nvicDisableVector(PVD_IRQn);
NVICDisableVector(RTC_Alarm_IRQn); nvicDisableVector(RTC_Alarm_IRQn);
#if defined(STM32L1XX_MD) #if defined(STM32L1XX_MD)
/* EXTI vectors specific to STM32L1xx.*/ /* EXTI vectors specific to STM32L1xx.*/
NVICDisableVector(USB_FS_WKUP_IRQn); nvicDisableVector(USB_FS_WKUP_IRQn);
NVICDisableVector(TAMPER_STAMP_IRQn); nvicDisableVector(TAMPER_STAMP_IRQn);
NVICDisableVector(RTC_WKUP_IRQn); nvicDisableVector(RTC_WKUP_IRQn);
NVICDisableVector(COMP_IRQn); nvicDisableVector(COMP_IRQn);
#elif defined(STM32F2XX) || defined(STM32F4XX) #elif defined(STM32F2XX) || defined(STM32F4XX)
/* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/
NVICDisableVector(OTG_FS_WKUP_IRQn); nvicDisableVector(OTG_FS_WKUP_IRQn);
NVICDisableVector(ETH_WKUP_IRQn); nvicDisableVector(ETH_WKUP_IRQn);
NVICDisableVector(OTG_HS_WKUP_IRQn); nvicDisableVector(OTG_HS_WKUP_IRQn);
NVICDisableVector(TAMP_STAMP_IRQn); nvicDisableVector(TAMP_STAMP_IRQn);
NVICDisableVector(RTC_WKUP_IRQn); nvicDisableVector(RTC_WKUP_IRQn);
#elif defined(STM32F10X_CL) #elif defined(STM32F10X_CL)
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/ /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
NVICDisableVector(OTG_FS_WKUP_IRQn); nvicDisableVector(OTG_FS_WKUP_IRQn);
NVICDisableVector(ETH_WKUP_IRQn); nvicDisableVector(ETH_WKUP_IRQn);
#else #else
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
NVICDisableVector(USB_FS_WKUP_IRQn); nvicDisableVector(USB_FS_WKUP_IRQn);
#endif #endif
} }
EXTI->EMR = 0; EXTI->EMR = 0;

24
os/hal/platforms/STM32/gpt_lld.c
View File

@ -270,7 +270,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
rccEnableTIM1(FALSE); rccEnableTIM1(FALSE);
rccResetTIM1(); rccResetTIM1();
NVICEnableVector(TIM1_UP_IRQn, nvicEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2; gptp->clock = STM32_TIMCLK2;
} }
@ -279,7 +279,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
rccEnableTIM2(FALSE); rccEnableTIM2(FALSE);
rccResetTIM2(); rccResetTIM2();
NVICEnableVector(TIM2_IRQn, nvicEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
} }
@ -288,7 +288,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
rccEnableTIM3(FALSE); rccEnableTIM3(FALSE);
rccResetTIM3(); rccResetTIM3();
NVICEnableVector(TIM3_IRQn, nvicEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
} }
@ -297,7 +297,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
rccEnableTIM4(FALSE); rccEnableTIM4(FALSE);
rccResetTIM4(); rccResetTIM4();
NVICEnableVector(TIM4_IRQn, nvicEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
} }
@ -307,7 +307,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD5 == gptp) { if (&GPTD5 == gptp) {
rccEnableTIM5(FALSE); rccEnableTIM5(FALSE);
rccResetTIM5(); rccResetTIM5();
NVICEnableVector(TIM5_IRQn, nvicEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
} }
@ -317,7 +317,7 @@ void gpt_lld_start(GPTDriver *gptp) {
if (&GPTD8 == gptp) { if (&GPTD8 == gptp) {
rccEnableTIM8(FALSE); rccEnableTIM8(FALSE);
rccResetTIM8(); rccResetTIM8();
NVICEnableVector(TIM8_UP_IRQn, nvicEnableVector(TIM8_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2; gptp->clock = STM32_TIMCLK2;
} }
@ -352,37 +352,37 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if STM32_GPT_USE_TIM1 #if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
NVICDisableVector(TIM1_UP_IRQn); nvicDisableVector(TIM1_UP_IRQn);
rccDisableTIM1(FALSE); rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM2 #if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
NVICDisableVector(TIM2_IRQn); nvicDisableVector(TIM2_IRQn);
rccDisableTIM2(FALSE); rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM3 #if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
NVICDisableVector(TIM3_IRQn); nvicDisableVector(TIM3_IRQn);
rccDisableTIM3(FALSE); rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM4 #if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
NVICDisableVector(TIM4_IRQn); nvicDisableVector(TIM4_IRQn);
rccDisableTIM4(FALSE); rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM5 #if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) { if (&GPTD5 == gptp) {
NVICDisableVector(TIM5_IRQn); nvicDisableVector(TIM5_IRQn);
rccDisableTIM5(FALSE); rccDisableTIM5(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM8 #if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) { if (&GPTD8 == gptp) {
NVICDisableVector(TIM8_UP_IRQn); nvicDisableVector(TIM8_UP_IRQn);
rccDisableTIM8(FALSE); rccDisableTIM8(FALSE);
} }
#endif #endif

24
os/hal/platforms/STM32/i2c_lld.c
View File

@ -384,9 +384,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
(void *)i2cp); (void *)i2cp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableI2C1(FALSE); rccEnableI2C1(FALSE);
NVICEnableVector(I2C1_EV_IRQn, nvicEnableVector(I2C1_EV_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
NVICEnableVector(I2C1_ER_IRQn, nvicEnableVector(I2C1_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | \ i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | \
@ -410,9 +410,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
(void *)i2cp); (void *)i2cp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableI2C2(FALSE); rccEnableI2C2(FALSE);
NVICEnableVector(I2C2_EV_IRQn, nvicEnableVector(I2C2_EV_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
NVICEnableVector(I2C2_ER_IRQn, nvicEnableVector(I2C2_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
@ -435,9 +435,9 @@ void i2c_lld_start(I2CDriver *i2cp) {
(void *)i2cp); (void *)i2cp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableI2C3(FALSE); rccEnableI2C3(FALSE);
NVICEnableVector(I2C3_EV_IRQn, nvicEnableVector(I2C3_EV_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
NVICEnableVector(I2C3_ER_IRQn, nvicEnableVector(I2C3_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
@ -705,24 +705,24 @@ void i2c_lld_stop(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C1 #if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
NVICDisableVector(I2C1_EV_IRQn); nvicDisableVector(I2C1_EV_IRQn);
NVICDisableVector(I2C1_ER_IRQn); nvicDisableVector(I2C1_ER_IRQn);
rccDisableI2C1(FALSE); rccDisableI2C1(FALSE);
} }
#endif #endif
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) { if (&I2CD2 == i2cp) {
NVICDisableVector(I2C2_EV_IRQn); nvicDisableVector(I2C2_EV_IRQn);
NVICDisableVector(I2C2_ER_IRQn); nvicDisableVector(I2C2_ER_IRQn);
rccDisableI2C2(FALSE); rccDisableI2C2(FALSE);
} }
#endif #endif
#if STM32_I2C_USE_I2C3 #if STM32_I2C_USE_I2C3
if (&I2CD3 == i2cp) { if (&I2CD3 == i2cp) {
NVICDisableVector(I2C3_EV_IRQn); nvicDisableVector(I2C3_EV_IRQn);
NVICDisableVector(I2C3_ER_IRQn); nvicDisableVector(I2C3_ER_IRQn);
rccDisableI2C3(FALSE); rccDisableI2C3(FALSE);
} }
#endif #endif

24
os/hal/platforms/STM32/icu_lld.c
View File

@ -289,7 +289,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD1 == icup) { if (&ICUD1 == icup) {
rccEnableTIM1(FALSE); rccEnableTIM1(FALSE);
rccResetTIM1(); rccResetTIM1();
NVICEnableVector(TIM1_CC_IRQn, nvicEnableVector(TIM1_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK2; icup->clock = STM32_TIMCLK2;
} }
@ -298,7 +298,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD2 == icup) { if (&ICUD2 == icup) {
rccEnableTIM2(FALSE); rccEnableTIM2(FALSE);
rccResetTIM2(); rccResetTIM2();
NVICEnableVector(TIM2_IRQn, nvicEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK1; icup->clock = STM32_TIMCLK1;
} }
@ -307,7 +307,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD3 == icup) { if (&ICUD3 == icup) {
rccEnableTIM3(FALSE); rccEnableTIM3(FALSE);
rccResetTIM3(); rccResetTIM3();
NVICEnableVector(TIM3_IRQn, nvicEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK1; icup->clock = STM32_TIMCLK1;
} }
@ -316,7 +316,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD4 == icup) { if (&ICUD4 == icup) {
rccEnableTIM4(FALSE); rccEnableTIM4(FALSE);
rccResetTIM4(); rccResetTIM4();
NVICEnableVector(TIM4_IRQn, nvicEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK1; icup->clock = STM32_TIMCLK1;
} }
@ -326,7 +326,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD5 == icup) { if (&ICUD5 == icup) {
rccEnableTIM5(FALSE); rccEnableTIM5(FALSE);
rccResetTIM5(); rccResetTIM5();
NVICEnableVector(TIM5_IRQn, nvicEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK1; icup->clock = STM32_TIMCLK1;
} }
@ -335,7 +335,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD8 == icup) { if (&ICUD8 == icup) {
rccEnableTIM5(FALSE); rccEnableTIM5(FALSE);
rccResetTIM5(); rccResetTIM5();
NVICEnableVector(TIM8_CC_IRQn, nvicEnableVector(TIM8_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK2; icup->clock = STM32_TIMCLK2;
} }
@ -395,38 +395,38 @@ void icu_lld_stop(ICUDriver *icup) {
#if STM32_ICU_USE_TIM1 #if STM32_ICU_USE_TIM1
if (&ICUD1 == icup) { if (&ICUD1 == icup) {
NVICDisableVector(TIM1_CC_IRQn); nvicDisableVector(TIM1_CC_IRQn);
rccDisableTIM1(FALSE); rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM2 #if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) { if (&ICUD2 == icup) {
NVICDisableVector(TIM2_IRQn); nvicDisableVector(TIM2_IRQn);
rccDisableTIM2(FALSE); rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM3 #if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) { if (&ICUD3 == icup) {
NVICDisableVector(TIM3_IRQn); nvicDisableVector(TIM3_IRQn);
rccDisableTIM3(FALSE); rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM4 #if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) { if (&ICUD4 == icup) {
NVICDisableVector(TIM4_IRQn); nvicDisableVector(TIM4_IRQn);
rccDisableTIM4(FALSE); rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM5 #if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) { if (&ICUD5 == icup) {
NVICDisableVector(TIM5_IRQn); nvicDisableVector(TIM5_IRQn);
rccDisableTIM5(FALSE); rccDisableTIM5(FALSE);
} }
#endif #endif
} }
#if STM32_ICU_USE_TIM8 #if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) { if (&ICUD8 == icup) {
NVICDisableVector(TIM8_CC_IRQn); nvicDisableVector(TIM8_CC_IRQn);
rccDisableTIM8(FALSE); rccDisableTIM8(FALSE);
} }
#endif #endif

32
os/hal/platforms/STM32/pwm_lld.c
View File

@ -351,9 +351,9 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD1 == pwmp) { if (&PWMD1 == pwmp) {
rccEnableTIM1(FALSE); rccEnableTIM1(FALSE);
rccResetTIM1(); rccResetTIM1();
NVICEnableVector(TIM1_UP_IRQn, nvicEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
NVICEnableVector(TIM1_CC_IRQn, nvicEnableVector(TIM1_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK2; pwmp->clock = STM32_TIMCLK2;
} }
@ -362,7 +362,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD2 == pwmp) { if (&PWMD2 == pwmp) {
rccEnableTIM2(FALSE); rccEnableTIM2(FALSE);
rccResetTIM2(); rccResetTIM2();
NVICEnableVector(TIM2_IRQn, nvicEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK1; pwmp->clock = STM32_TIMCLK1;
} }
@ -371,7 +371,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD3 == pwmp) { if (&PWMD3 == pwmp) {
rccEnableTIM3(FALSE); rccEnableTIM3(FALSE);
rccResetTIM3(); rccResetTIM3();
NVICEnableVector(TIM3_IRQn, nvicEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK1; pwmp->clock = STM32_TIMCLK1;
} }
@ -380,7 +380,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD4 == pwmp) { if (&PWMD4 == pwmp) {
rccEnableTIM4(FALSE); rccEnableTIM4(FALSE);
rccResetTIM4(); rccResetTIM4();
NVICEnableVector(TIM4_IRQn, nvicEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK1; pwmp->clock = STM32_TIMCLK1;
} }
@ -390,7 +390,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD5 == pwmp) { if (&PWMD5 == pwmp) {
rccEnableTIM5(FALSE); rccEnableTIM5(FALSE);
rccResetTIM5(); rccResetTIM5();
NVICEnableVector(TIM5_IRQn, nvicEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK1; pwmp->clock = STM32_TIMCLK1;
} }
@ -399,9 +399,9 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD8 == pwmp) { if (&PWMD8 == pwmp) {
rccEnableTIM8(FALSE); rccEnableTIM8(FALSE);
rccResetTIM8(); rccResetTIM8();
NVICEnableVector(TIM8_UP_IRQn, nvicEnableVector(TIM8_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
NVICEnableVector(TIM8_CC_IRQn, nvicEnableVector(TIM8_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
pwmp->clock = STM32_TIMCLK2; pwmp->clock = STM32_TIMCLK2;
} }
@ -545,39 +545,39 @@ void pwm_lld_stop(PWMDriver *pwmp) {
#if STM32_PWM_USE_TIM1 #if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) { if (&PWMD1 == pwmp) {
NVICDisableVector(TIM1_UP_IRQn); nvicDisableVector(TIM1_UP_IRQn);
NVICDisableVector(TIM1_CC_IRQn); nvicDisableVector(TIM1_CC_IRQn);
rccDisableTIM1(FALSE); rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM2 #if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) { if (&PWMD2 == pwmp) {
NVICDisableVector(TIM2_IRQn); nvicDisableVector(TIM2_IRQn);
rccDisableTIM2(FALSE); rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM3 #if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) { if (&PWMD3 == pwmp) {
NVICDisableVector(TIM3_IRQn); nvicDisableVector(TIM3_IRQn);
rccDisableTIM3(FALSE); rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM4 #if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) { if (&PWMD4 == pwmp) {
NVICDisableVector(TIM4_IRQn); nvicDisableVector(TIM4_IRQn);
rccDisableTIM4(FALSE); rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM5 #if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) { if (&PWMD5 == pwmp) {
NVICDisableVector(TIM5_IRQn); nvicDisableVector(TIM5_IRQn);
rccDisableTIM5(FALSE); rccDisableTIM5(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM8 #if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) { if (&PWMD8 == pwmp) {
NVICDisableVector(TIM8_UP_IRQn); nvicDisableVector(TIM8_UP_IRQn);
NVICDisableVector(TIM8_CC_IRQn); nvicDisableVector(TIM8_CC_IRQn);
rccDisableTIM8(FALSE); rccDisableTIM8(FALSE);
} }
#endif #endif

4
os/hal/platforms/STM32/sdc_lld.c
View File

@ -441,7 +441,7 @@ void sdc_lld_start(SDCDriver *sdcp) {
/* Note, the DMA must be enabled before the IRQs.*/ /* Note, the DMA must be enabled before the IRQs.*/
dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL); dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL);
dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO);
NVICEnableVector(SDIO_IRQn, nvicEnableVector(SDIO_IRQn,
CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
rccEnableSDIO(FALSE); rccEnableSDIO(FALSE);
} }
@ -468,7 +468,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
SDIO->DTIMER = 0; SDIO->DTIMER = 0;
/* Clock deactivation.*/ /* Clock deactivation.*/
NVICDisableVector(SDIO_IRQn); nvicDisableVector(SDIO_IRQn);
dmaStreamRelease(STM32_DMA2_STREAM4); dmaStreamRelease(STM32_DMA2_STREAM4);
rccDisableSDIO(FALSE); rccDisableSDIO(FALSE);
} }

24
os/hal/platforms/STM32/serial_lld.c
View File

@ -415,42 +415,42 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
#if STM32_SERIAL_USE_USART1 #if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) { if (&SD1 == sdp) {
rccEnableUSART1(FALSE); rccEnableUSART1(FALSE);
NVICEnableVector(USART1_IRQn, nvicEnableVector(USART1_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_USART2 #if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD2 == sdp) {
rccEnableUSART2(FALSE); rccEnableUSART2(FALSE);
NVICEnableVector(USART2_IRQn, nvicEnableVector(USART2_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_USART3 #if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) { if (&SD3 == sdp) {
rccEnableUSART3(FALSE); rccEnableUSART3(FALSE);
NVICEnableVector(USART3_IRQn, nvicEnableVector(USART3_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_UART4 #if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
rccEnableUART4(FALSE); rccEnableUART4(FALSE);
NVICEnableVector(UART4_IRQn, nvicEnableVector(UART4_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_UART5 #if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) { if (&SD5 == sdp) {
rccEnableUART5(FALSE); rccEnableUART5(FALSE);
NVICEnableVector(UART5_IRQn, nvicEnableVector(UART5_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_USART6 #if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) { if (&SD6 == sdp) {
rccEnableUSART6(FALSE); rccEnableUSART6(FALSE);
NVICEnableVector(USART6_IRQn, nvicEnableVector(USART6_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
} }
#endif #endif
@ -474,42 +474,42 @@ void sd_lld_stop(SerialDriver *sdp) {
#if STM32_SERIAL_USE_USART1 #if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) { if (&SD1 == sdp) {
rccDisableUSART1(FALSE); rccDisableUSART1(FALSE);
NVICDisableVector(USART1_IRQn); nvicDisableVector(USART1_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_USART2 #if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD2 == sdp) {
rccDisableUSART2(FALSE); rccDisableUSART2(FALSE);
NVICDisableVector(USART2_IRQn); nvicDisableVector(USART2_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_USART3 #if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) { if (&SD3 == sdp) {
rccDisableUSART3(FALSE); rccDisableUSART3(FALSE);
NVICDisableVector(USART3_IRQn); nvicDisableVector(USART3_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_UART4 #if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
rccDisableUART4(FALSE); rccDisableUART4(FALSE);
NVICDisableVector(UART4_IRQn); nvicDisableVector(UART4_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_UART5 #if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) { if (&SD5 == sdp) {
rccDisableUART5(FALSE); rccDisableUART5(FALSE);
NVICDisableVector(UART5_IRQn); nvicDisableVector(UART5_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_USART6 #if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) { if (&SD6 == sdp) {
rccDisableUSART6(FALSE); rccDisableUSART6(FALSE);
NVICDisableVector(USART6_IRQn); nvicDisableVector(USART6_IRQn);
return; return;
} }
#endif #endif

12
os/hal/platforms/STM32/uart_lld.c
View File

@ -396,7 +396,7 @@ void uart_lld_start(UARTDriver *uartp) {
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
rccEnableUSART1(FALSE); rccEnableUSART1(FALSE);
NVICEnableVector(USART1_IRQn, nvicEnableVector(USART1_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
@ -417,7 +417,7 @@ void uart_lld_start(UARTDriver *uartp) {
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableUSART2(FALSE); rccEnableUSART2(FALSE);
NVICEnableVector(USART2_IRQn, nvicEnableVector(USART2_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
@ -438,7 +438,7 @@ void uart_lld_start(UARTDriver *uartp) {
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
rccEnableUSART3(FALSE); rccEnableUSART3(FALSE);
NVICEnableVector(USART3_IRQn, nvicEnableVector(USART3_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
@ -475,7 +475,7 @@ void uart_lld_stop(UARTDriver *uartp) {
#if STM32_UART_USE_USART1 #if STM32_UART_USE_USART1
if (&UARTD1 == uartp) { if (&UARTD1 == uartp) {
NVICDisableVector(USART1_IRQn); nvicDisableVector(USART1_IRQn);
rccDisableUSART1(FALSE); rccDisableUSART1(FALSE);
return; return;
} }
@ -483,7 +483,7 @@ void uart_lld_stop(UARTDriver *uartp) {
#if STM32_UART_USE_USART2 #if STM32_UART_USE_USART2
if (&UARTD2 == uartp) { if (&UARTD2 == uartp) {
NVICDisableVector(USART2_IRQn); nvicDisableVector(USART2_IRQn);
rccDisableUSART2(FALSE); rccDisableUSART2(FALSE);
return; return;
} }
@ -491,7 +491,7 @@ void uart_lld_stop(UARTDriver *uartp) {
#if STM32_UART_USE_USART3 #if STM32_UART_USE_USART3
if (&UARTD3 == uartp) { if (&UARTD3 == uartp) {
NVICDisableVector(USART3_IRQn); nvicDisableVector(USART3_IRQn);
rccDisableUSART3(FALSE); rccDisableUSART3(FALSE);
return; return;
} }

2
os/hal/platforms/STM32F1xx/hal_lld.c
View File

@ -29,8 +29,6 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#define AIRCR_VECTKEY 0x05FA0000
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/

4
os/hal/platforms/STM32F1xx/stm32_dma.c
View File

@ -451,7 +451,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/ /* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) if (func != NULL)
NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE; return FALSE;
} }
@ -478,7 +478,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
"dmaRelease(), #1", "not allocated"); "dmaRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/ /* Disables the associated IRQ vector.*/
NVICDisableVector(dmastp->vector); nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/ /* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex); dma_streams_mask &= ~(1 << dmastp->selfindex);

2
os/hal/platforms/STM32F2xx/hal_lld.c
View File

@ -29,8 +29,6 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#define AIRCR_VECTKEY 0x05FA0000
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/

4
os/hal/platforms/STM32F2xx/stm32_dma.c
View File

@ -493,7 +493,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/ /* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) if (func != NULL)
NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE; return FALSE;
} }
@ -520,7 +520,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
"dmaRelease(), #1", "not allocated"); "dmaRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/ /* Disables the associated IRQ vector.*/
NVICDisableVector(dmastp->vector); nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/ /* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex); dma_streams_mask &= ~(1 << dmastp->selfindex);

2
os/hal/platforms/STM32F4xx/adc_lld.c
View File

@ -220,7 +220,7 @@ void adc_lld_init(void) {
/* The shared vector is initialized on driver initialization and never /* The shared vector is initialized on driver initialization and never
disabled.*/ disabled.*/
NVICEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
} }
/** /**

2
os/hal/platforms/STM32F4xx/hal_lld.c
View File

@ -29,8 +29,6 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#define AIRCR_VECTKEY 0x05FA0000
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/

4
os/hal/platforms/STM32F4xx/stm32_dma.c
View File

@ -489,7 +489,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/ /* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) if (func != NULL)
NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE; return FALSE;
} }
@ -516,7 +516,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
"dmaRelease(), #1", "not allocated"); "dmaRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/ /* Disables the associated IRQ vector.*/
NVICDisableVector(dmastp->vector); nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/ /* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex); dma_streams_mask &= ~(1 << dmastp->selfindex);

2
os/hal/platforms/STM32L1xx/adc_lld.c
View File

@ -135,7 +135,7 @@ void adc_lld_init(void) {
/* The shared vector is initialized on driver initialization and never /* The shared vector is initialized on driver initialization and never
disabled.*/ disabled.*/
NVICEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
} }
/** /**

2
os/hal/platforms/STM32L1xx/hal_lld.c
View File

@ -29,8 +29,6 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#define AIRCR_VECTKEY 0x05FA0000
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/

4
os/hal/platforms/STM32L1xx/stm32_dma.c
View File

@ -307,7 +307,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/ /* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) if (func != NULL)
NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE; return FALSE;
} }
@ -334,7 +334,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
"dmaRelease(), #1", "not allocated"); "dmaRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/ /* Disables the associated IRQ vector.*/
NVICDisableVector(dmastp->vector); nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/ /* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex); dma_streams_mask &= ~(1 << dmastp->selfindex);

3
os/ports/GCC/ARMCMx/LPC11xx/port.mk
View File

@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
$(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \ $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
PORTASM = PORTASM =
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
${CHIBIOS}/os/ports/common/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx \ ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx

3
os/ports/GCC/ARMCMx/LPC13xx/port.mk
View File

@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
$(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \ $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
PORTASM = PORTASM =
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
${CHIBIOS}/os/ports/common/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx \ ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx

3
os/ports/GCC/ARMCMx/STM32F1xx/port.mk
View File

@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \ $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
PORTASM = PORTASM =
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
${CHIBIOS}/os/ports/common/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx \ ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx

3
os/ports/GCC/ARMCMx/STM32F4xx/port.mk
View File

@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \ $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
PORTASM = PORTASM =
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
${CHIBIOS}/os/ports/common/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx \ ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx

3
os/ports/GCC/ARMCMx/STM32L1xx/port.mk
View File

@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \ $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
PORTASM = PORTASM =
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
${CHIBIOS}/os/ports/common/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx \ ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx

20
os/ports/GCC/ARMCMx/chcore.h
View File

@ -143,17 +143,6 @@
#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" #error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif #endif
/**
* @brief Stack alignment enforcement.
* @note The default value is 64 in order to comply with EABI, reducing
* the value to 32 can save some RAM space if you don't care about
* binary compatibility with EABI compiled libraries.
* @note Allowed values are 32 or 64.
*/
#if !defined(CORTEX_STACK_ALIGNMENT)
#define CORTEX_STACK_ALIGNMENT 64
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Port derived parameters (common). */ /* Port derived parameters (common). */
/*===========================================================================*/ /*===========================================================================*/
@ -189,19 +178,16 @@
/** /**
* @brief Stack and memory alignment enforcement. * @brief Stack and memory alignment enforcement.
* @note In this architecture the stack alignment is enforced to 64 bits,
* 32 bits alignment is supported by hardware but deprecated by ARM,
* the implementation choice is to not offer the option.
*/ */
#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__)
#if defined(__DOXYGEN__) #if defined(__DOXYGEN__)
/* Dummy declaration, for Doxygen only.*/ /* Dummy declaration, for Doxygen only.*/
typedef uint64_t stkalign_t; typedef uint64_t stkalign_t;
#else #else
typedef uint64_t stkalign_t __attribute__ ((aligned (8))); typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
#endif #endif
#elif CORTEX_STACK_ALIGNMENT == 32
typedef uint32_t stkalign_t __attribute__ ((aligned (4)));
#else
#error "invalid stack alignment selected"
#endif
#if defined(__DOXYGEN__) #if defined(__DOXYGEN__)
/** /**

4
os/ports/GCC/ARMCMx/chcore_v6m.h
View File

@ -161,9 +161,9 @@ struct intctx {
*/ */
#define port_init() { \ #define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
} }

59
os/ports/GCC/ARMCMx/chcore_v7m.c
View File

@ -28,17 +28,9 @@
#include "ch.h" #include "ch.h"
#if !CH_OPTIMIZE_SPEED /*===========================================================================*/
void _port_lock(void) { /* Port interrupt handlers. */
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; /*===========================================================================*/
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
void _port_unlock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
#endif
/** /**
* @brief System Timer vector. * @brief System Timer vector.
@ -109,6 +101,10 @@ void PendSVVector(void) {
} }
#endif /* CORTEX_SIMPLIFIED_PRIORITY */ #endif /* CORTEX_SIMPLIFIED_PRIORITY */
/*===========================================================================*/
/* Port exported functions. */
/*===========================================================================*/
/** /**
* @brief Port-related initialization code. * @brief Port-related initialization code.
*/ */
@ -141,20 +137,30 @@ void _port_init(void) {
#endif #endif
/* Initialization of the system vectors used by the port.*/ /* Initialization of the system vectors used by the port.*/
NVICSetSystemHandlerPriority(HANDLER_SVCALL, nvicSetSystemHandlerPriority(HANDLER_SVCALL,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
NVICSetSystemHandlerPriority(HANDLER_PENDSV, nvicSetSystemHandlerPriority(HANDLER_PENDSV,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
} }
#if !CH_OPTIMIZE_SPEED
void _port_lock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
void _port_unlock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
#endif
/** /**
* @brief Exception exit redirection to _port_switch_from_isr(). * @brief Exception exit redirection to _port_switch_from_isr().
*/ */
void _port_irq_epilogue(void) { void _port_irq_epilogue(void) {
#if CORTEX_USE_FPU
uint32_t fpccr;
#endif
port_lock_from_isr(); port_lock_from_isr();
if ((SCB_ICSR & ICSR_RETTOBASE)) { if ((SCB_ICSR & ICSR_RETTOBASE)) {
@ -187,14 +193,17 @@ void _port_irq_epilogue(void) {
} }
#if CORTEX_USE_FPU #if CORTEX_USE_FPU
/* Saving the special register SCB_FPCCR into the reserved offset of {
the Cortex-M4 exception frame.*/ uint32_t fpccr;
(ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
#endif /* Saving the special register SCB_FPCCR into the reserved offset of
#if CORTEX_USE_FPU the Cortex-M4 exception frame.*/
/* Now the FPCCR is modified in order to not restore the FPU status (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
from the artificial return context.*/
SCB_FPCCR = fpccr | FPCCR_LSPACT; /* Now the FPCCR is modified in order to not restore the FPU status
from the artificial return context.*/
SCB_FPCCR = fpccr | FPCCR_LSPACT;
}
#endif #endif
/* Note, returning without unlocking is intentional, this is done in /* Note, returning without unlocking is intentional, this is done in

4
os/ports/IAR/ARMCMx/chcore_v6m.h
View File

@ -159,9 +159,9 @@ struct intctx {
*/ */
#define port_init() { \ #define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
} }

6
os/ports/IAR/ARMCMx/chcore_v7m.h
View File

@ -201,11 +201,11 @@ struct intctx {
#define port_init() { \ #define port_init() { \
SCB_VTOR = CORTEX_VTOR_INIT; \ SCB_VTOR = CORTEX_VTOR_INIT; \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ nvicSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
} }

76
os/ports/IAR/ARMCMx/nvic.c
View File

@ -1,76 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file IAR/ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code.
*
* @addtogroup IAR_ARMCMx_NVIC
* @{
*/
#include "ch.h"
#include "nvic.h"
/**
* @brief Sets the priority of an interrupt handler and enables it.
*
* @param n the interrupt number
* @param prio the interrupt priority mask
*
* @note The parameters are not tested for correctness.
*/
void NVICEnableVector(uint32_t n, uint32_t prio) {
unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
}
/**
* @brief Disables an interrupt handler.
*
* @param n the interrupt number
*
* @note The parameters are not tested for correctness.
*/
void NVICDisableVector(uint32_t n) {
unsigned sh = (n & 3) << 3;
NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);
}
/**
* @brief Changes the priority of a system handler.
*
* @param handler the system handler number
* @param prio the system handler priority mask
* @note The parameters are not tested for correctness.
*/
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
unsigned sh = (handler & 3) * 8;
SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &
~(0xFF << sh)) | (prio << sh);
}
/** @} */

193
os/ports/IAR/ARMCMx/nvic.h
View File

@ -1,193 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file IAR/ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures.
*
* @addtogroup IAR_ARMCMx_NVIC
* @{
*/
#ifndef _NVIC_H_
#define _NVIC_H_
/*
* System vector constants for @p NVICSetSystemHandlerPriority().
*/
#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
#define HANDLER_RESERVED_3 3
#define HANDLER_RESERVED_4 4
#define HANDLER_RESERVED_5 5
#define HANDLER_RESERVED_6 6
#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
#define HANDLER_RESERVED_9 9
#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
/**
* @brief NVIC ITCR register.
*/
#define NVIC_ITCR (*((IOREG32 *)0xE000E004))
/**
* @brief NVIC STIR register.
*/
#define NVIC_STIR (*((IOREG32 *)0xE000EF00))
/**
* @brief Structure representing the SYSTICK I/O space.
*/
typedef struct {
IOREG32 CSR;
IOREG32 RVR;
IOREG32 CVR;
IOREG32 CBVR;
} CM3_ST;
/**
* @brief SYSTICK peripheral base address.
*/
#define STBase ((CM3_ST *)0xE000E010)
#define ST_CSR (STBase->CSR)
#define ST_RVR (STBase->RVR)
#define ST_CVR (STBase->CVR)
#define ST_CBVR (STBase->CBVR)
#define CSR_ENABLE_MASK (0x1 << 0)
#define ENABLE_OFF_BITS (0 << 0)
#define ENABLE_ON_BITS (1 << 0)
#define CSR_TICKINT_MASK (0x1 << 1)
#define TICKINT_DISABLED_BITS (0 << 1)
#define TICKINT_ENABLED_BITS (1 << 1)
#define CSR_CLKSOURCE_MASK (0x1 << 2)
#define CLKSOURCE_EXT_BITS (0 << 2)
#define CLKSOURCE_CORE_BITS (1 << 2)
#define CSR_COUNTFLAG_MASK (0x1 << 16)
#define RVR_RELOAD_MASK (0xFFFFFF << 0)
#define CVR_CURRENT_MASK (0xFFFFFF << 0)
#define CBVR_TENMS_MASK (0xFFFFFF << 0)
#define CBVR_SKEW_MASK (0x1 << 30)
#define CBVR_NOREF_MASK (0x1 << 31)
/**
* @brief Structure representing the NVIC I/O space.
*/
typedef struct {
IOREG32 ISER[8];
IOREG32 unused1[24];
IOREG32 ICER[8];
IOREG32 unused2[24];
IOREG32 ISPR[8];
IOREG32 unused3[24];
IOREG32 ICPR[8];
IOREG32 unused4[24];
IOREG32 IABR[8];
IOREG32 unused5[56];
IOREG32 IPR[60];
} CM3_NVIC;
/**
* @brief NVIC peripheral base address.
*/
#define NVICBase ((CM3_NVIC *)0xE000E100)
#define NVIC_ISER(n) (NVICBase->ISER[n])
#define NVIC_ICER(n) (NVICBase->ICER[n])
#define NVIC_ISPR(n) (NVICBase->ISPR[n])
#define NVIC_ICPR(n) (NVICBase->ICPR[n])
#define NVIC_IABR(n) (NVICBase->IABR[n])
#define NVIC_IPR(n) (NVICBase->IPR[n])
/**
* @brief Structure representing the System Control Block I/O space.
*/
typedef struct {
IOREG32 CPUID;
IOREG32 ICSR;
IOREG32 VTOR;
IOREG32 AIRCR;
IOREG32 SCR;
IOREG32 CCR;
IOREG32 SHPR[3];
IOREG32 SHCSR;
IOREG32 CFSR;
IOREG32 HFSR;
IOREG32 DFSR;
IOREG32 MMFAR;
IOREG32 BFAR;
IOREG32 AFSR;
} CM3_SCB;
/**
* @brief SCB peripheral base address.
*/
#define SCBBase ((CM3_SCB *)0xE000ED00)
#define SCB_CPUID (SCBBase->CPUID)
#define SCB_ICSR (SCBBase->ICSR)
#define SCB_VTOR (SCBBase->VTOR)
#define SCB_AIRCR (SCBBase->AIRCR)
#define SCB_SCR (SCBBase->SCR)
#define SCB_CCR (SCBBase->CCR)
#define SCB_SHPR(n) (SCBBase->SHPR[n])
#define SCB_SHCSR (SCBBase->SHCSR)
#define SCB_CFSR (SCBBase->CFSR)
#define SCB_HFSR (SCBBase->HFSR)
#define SCB_DFSR (SCBBase->DFSR)
#define SCB_MMFAR (SCBBase->MMFAR)
#define SCB_BFAR (SCBBase->BFAR)
#define SCB_AFSR (SCBBase->AFSR)
#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
#define ICSR_RETTOBASE (0x1 << 11)
#define ICSR_VECTPENDING_MASK (0x1FF << 12)
#define ICSR_ISRPENDING (0x1 << 22)
#define ICSR_ISRPREEMPT (0x1 << 23)
#define ICSR_PENDSTCLR (0x1 << 25)
#define ICSR_PENDSTSET (0x1 << 26)
#define ICSR_PENDSVCLR (0x1 << 27)
#define ICSR_PENDSVSET (0x1 << 28)
#define ICSR_NMIPENDSET (0x1 << 31)
#define AIRCR_VECTKEY 0x05FA0000
#define AIRCR_PRIGROUP_MASK (0x7 << 8)
#define AIRCR_PRIGROUP(n) ((n) << 8)
#ifdef __cplusplus
extern "C" {
#endif
void NVICEnableVector(uint32_t n, uint32_t prio);
void NVICDisableVector(uint32_t n);
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_H_ */
/** @} */

4
os/ports/RVCT/ARMCMx/chcore_v6m.h
View File

@ -159,9 +159,9 @@ struct intctx {
*/ */
#define port_init() { \ #define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
} }

6
os/ports/RVCT/ARMCMx/chcore_v7m.h
View File

@ -201,11 +201,11 @@ struct intctx {
#define port_init() { \ #define port_init() { \
SCB_VTOR = CORTEX_VTOR_INIT; \ SCB_VTOR = CORTEX_VTOR_INIT; \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ nvicSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
} }

76
os/ports/RVCT/ARMCMx/nvic.c
View File

@ -1,76 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file RVCT/ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code.
*
* @addtogroup RVCT_ARMCMx_NVIC
* @{
*/
#include "ch.h"
#include "nvic.h"
/**
* @brief Sets the priority of an interrupt handler and enables it.
*
* @param n the interrupt number
* @param prio the interrupt priority mask
*
* @note The parameters are not tested for correctness.
*/
void NVICEnableVector(uint32_t n, uint32_t prio) {
unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
}
/**
* @brief Disables an interrupt handler.
*
* @param n the interrupt number
*
* @note The parameters are not tested for correctness.
*/
void NVICDisableVector(uint32_t n) {
unsigned sh = (n & 3) << 3;
NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);
}
/**
* @brief Changes the priority of a system handler.
*
* @param handler the system handler number
* @param prio the system handler priority mask
* @note The parameters are not tested for correctness.
*/
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
unsigned sh = (handler & 3) * 8;
SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &
~(0xFF << sh)) | (prio << sh);
}
/** @} */

193
os/ports/RVCT/ARMCMx/nvic.h
View File

@ -1,193 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file RVCT/ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures.
*
* @addtogroup RVCT_ARMCMx_NVIC
* @{
*/
#ifndef _NVIC_H_
#define _NVIC_H_
/*
* System vector constants for @p NVICSetSystemHandlerPriority().
*/
#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
#define HANDLER_RESERVED_3 3
#define HANDLER_RESERVED_4 4
#define HANDLER_RESERVED_5 5
#define HANDLER_RESERVED_6 6
#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
#define HANDLER_RESERVED_9 9
#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
/**
* @brief NVIC ITCR register.
*/
#define NVIC_ITCR (*((IOREG32 *)0xE000E004))
/**
* @brief NVIC STIR register.
*/
#define NVIC_STIR (*((IOREG32 *)0xE000EF00))
/**
* @brief Structure representing the SYSTICK I/O space.
*/
typedef struct {
IOREG32 CSR;
IOREG32 RVR;
IOREG32 CVR;
IOREG32 CBVR;
} CM3_ST;
/**
* @brief SYSTICK peripheral base address.
*/
#define STBase ((CM3_ST *)0xE000E010)
#define ST_CSR (STBase->CSR)
#define ST_RVR (STBase->RVR)
#define ST_CVR (STBase->CVR)
#define ST_CBVR (STBase->CBVR)
#define CSR_ENABLE_MASK (0x1 << 0)
#define ENABLE_OFF_BITS (0 << 0)
#define ENABLE_ON_BITS (1 << 0)
#define CSR_TICKINT_MASK (0x1 << 1)
#define TICKINT_DISABLED_BITS (0 << 1)
#define TICKINT_ENABLED_BITS (1 << 1)
#define CSR_CLKSOURCE_MASK (0x1 << 2)
#define CLKSOURCE_EXT_BITS (0 << 2)
#define CLKSOURCE_CORE_BITS (1 << 2)
#define CSR_COUNTFLAG_MASK (0x1 << 16)
#define RVR_RELOAD_MASK (0xFFFFFF << 0)
#define CVR_CURRENT_MASK (0xFFFFFF << 0)
#define CBVR_TENMS_MASK (0xFFFFFF << 0)
#define CBVR_SKEW_MASK (0x1 << 30)
#define CBVR_NOREF_MASK (0x1 << 31)
/**
* @brief Structure representing the NVIC I/O space.
*/
typedef struct {
IOREG32 ISER[8];
IOREG32 unused1[24];
IOREG32 ICER[8];
IOREG32 unused2[24];
IOREG32 ISPR[8];
IOREG32 unused3[24];
IOREG32 ICPR[8];
IOREG32 unused4[24];
IOREG32 IABR[8];
IOREG32 unused5[56];
IOREG32 IPR[60];
} CM3_NVIC;
/**
* @brief NVIC peripheral base address.
*/
#define NVICBase ((CM3_NVIC *)0xE000E100)
#define NVIC_ISER(n) (NVICBase->ISER[n])
#define NVIC_ICER(n) (NVICBase->ICER[n])
#define NVIC_ISPR(n) (NVICBase->ISPR[n])
#define NVIC_ICPR(n) (NVICBase->ICPR[n])
#define NVIC_IABR(n) (NVICBase->IABR[n])
#define NVIC_IPR(n) (NVICBase->IPR[n])
/**
* @brief Structure representing the System Control Block I/O space.
*/
typedef struct {
IOREG32 CPUID;
IOREG32 ICSR;
IOREG32 VTOR;
IOREG32 AIRCR;
IOREG32 SCR;
IOREG32 CCR;
IOREG32 SHPR[3];
IOREG32 SHCSR;
IOREG32 CFSR;
IOREG32 HFSR;
IOREG32 DFSR;
IOREG32 MMFAR;
IOREG32 BFAR;
IOREG32 AFSR;
} CM3_SCB;
/**
* @brief SCB peripheral base address.
*/
#define SCBBase ((CM3_SCB *)0xE000ED00)
#define SCB_CPUID (SCBBase->CPUID)
#define SCB_ICSR (SCBBase->ICSR)
#define SCB_VTOR (SCBBase->VTOR)
#define SCB_AIRCR (SCBBase->AIRCR)
#define SCB_SCR (SCBBase->SCR)
#define SCB_CCR (SCBBase->CCR)
#define SCB_SHPR(n) (SCBBase->SHPR[n])
#define SCB_SHCSR (SCBBase->SHCSR)
#define SCB_CFSR (SCBBase->CFSR)
#define SCB_HFSR (SCBBase->HFSR)
#define SCB_DFSR (SCBBase->DFSR)
#define SCB_MMFAR (SCBBase->MMFAR)
#define SCB_BFAR (SCBBase->BFAR)
#define SCB_AFSR (SCBBase->AFSR)
#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
#define ICSR_RETTOBASE (0x1 << 11)
#define ICSR_VECTPENDING_MASK (0x1FF << 12)
#define ICSR_ISRPENDING (0x1 << 22)
#define ICSR_ISRPREEMPT (0x1 << 23)
#define ICSR_PENDSTCLR (0x1 << 25)
#define ICSR_PENDSTSET (0x1 << 26)
#define ICSR_PENDSVCLR (0x1 << 27)
#define ICSR_PENDSVSET (0x1 << 28)
#define ICSR_NMIPENDSET (0x1 << 31)
#define AIRCR_VECTKEY 0x05FA0000
#define AIRCR_PRIGROUP_MASK (0x7 << 8)
#define AIRCR_PRIGROUP(n) ((n) << 8)
#ifdef __cplusplus
extern "C" {
#endif
void NVICEnableVector(uint32_t n, uint32_t prio);
void NVICDisableVector(uint32_t n);
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_H_ */
/** @} */

16
os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm3.h * @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V2.10 * @version V2.11
* @date 19. July 2011 * @date 08. September 2011
* *
* @note * @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved. * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
@ -97,8 +97,8 @@
#endif #endif
/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#define __FPU_USED 0 #define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
@ -376,8 +376,16 @@ typedef struct
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */ /* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */ /* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */

34
os/ports/GCC/ARMCMx/nvic.c → os/ports/common/ARMCMx/nvic.c
View File

@ -19,10 +19,10 @@
*/ */
/** /**
* @file GCC/ARMCMx/nvic.c * @file common/ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code. * @brief Cortex-Mx NVIC support code.
* *
* @addtogroup ARMCMx_NVIC * @addtogroup COMMON_ARMCMx_NVIC
* @{ * @{
*/ */
@ -30,14 +30,13 @@
#include "nvic.h" #include "nvic.h"
/** /**
* @brief Sets the priority of an interrupt handler and enables it. * @brief Sets the priority of an interrupt handler and enables it.
* @note The parameters are not tested for correctness.
* *
* @param n the interrupt number * @param[in] n the interrupt number
* @param prio the interrupt priority mask * @param[in] prio the interrupt priority mask
*
* @note The parameters are not tested for correctness.
*/ */
void NVICEnableVector(uint32_t n, uint32_t prio) { void nvicEnableVector(uint32_t n, uint32_t prio) {
unsigned sh = (n & 3) << 3; unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
@ -46,13 +45,12 @@ void NVICEnableVector(uint32_t n, uint32_t prio) {
} }
/** /**
* @brief Disables an interrupt handler. * @brief Disables an interrupt handler.
* @note The parameters are not tested for correctness.
* *
* @param n the interrupt number * @param[in] n the interrupt number
*
* @note The parameters are not tested for correctness.
*/ */
void NVICDisableVector(uint32_t n) { void nvicDisableVector(uint32_t n) {
unsigned sh = (n & 3) << 3; unsigned sh = (n & 3) << 3;
NVIC_ICER(n >> 5) = 1 << (n & 0x1F); NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
@ -60,13 +58,13 @@ void NVICDisableVector(uint32_t n) {
} }
/** /**
* @brief Changes the priority of a system handler. * @brief Changes the priority of a system handler.
* @note The parameters are not tested for correctness.
* *
* @param handler the system handler number * @param[in] handler the system handler number
* @param prio the system handler priority mask * @param[in] prio the system handler priority mask
* @note The parameters are not tested for correctness.
*/ */
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
unsigned sh = (handler & 3) * 8; unsigned sh = (handler & 3) * 8;
SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &

82
os/ports/GCC/ARMCMx/nvic.h → os/ports/common/ARMCMx/nvic.h
View File

@ -19,18 +19,19 @@
*/ */
/** /**
* @file GCC/ARMCMx/nvic.h * @file common/ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures. * @brief Cortex-Mx NVIC support macros and structures.
* *
* @addtogroup ARMCMx_NVIC * @addtogroup COMMON_ARMCMx_NVIC
* @{ * @{
*/ */
#ifndef _NVIC_H_ #ifndef _NVIC_H_
#define _NVIC_H_ #define _NVIC_H_
/* /**
* System vector constants for @p NVICSetSystemHandlerPriority(). * @name System vector numbers
* @{
*/ */
#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ #define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ #define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
@ -44,6 +45,7 @@
#define HANDLER_RESERVED_9 9 #define HANDLER_RESERVED_9 9
#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ #define HANDLER_PENDSV 10 /**< PENDSV vector id. */
#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ #define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
/** @} */
typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
@ -51,7 +53,7 @@ typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
/** /**
* @brief NVIC ITCR register. * @brief NVIC ITCR register.
*/ */
#define NVIC_ITCR (*((IOREG32 *)0xE000E004)) #define NVIC_ITCR (*((IOREG32 *)0xE000E004U))
/** /**
* @brief Structure representing the SYSTICK I/O space. * @brief Structure representing the SYSTICK I/O space.
@ -66,30 +68,30 @@ typedef struct {
/** /**
* @brief SYSTICK peripheral base address. * @brief SYSTICK peripheral base address.
*/ */
#define STBase ((CMx_ST *)0xE000E010) #define STBase ((CMx_ST *)0xE000E010U)
#define ST_CSR (STBase->CSR) #define ST_CSR (STBase->CSR)
#define ST_RVR (STBase->RVR) #define ST_RVR (STBase->RVR)
#define ST_CVR (STBase->CVR) #define ST_CVR (STBase->CVR)
#define ST_CBVR (STBase->CBVR) #define ST_CBVR (STBase->CBVR)
#define CSR_ENABLE_MASK (0x1 << 0) #define CSR_ENABLE_MASK (0x1U << 0)
#define ENABLE_OFF_BITS (0 << 0) #define ENABLE_OFF_BITS (0U << 0)
#define ENABLE_ON_BITS (1 << 0) #define ENABLE_ON_BITS (1U << 0)
#define CSR_TICKINT_MASK (0x1 << 1) #define CSR_TICKINT_MASK (0x1U << 1)
#define TICKINT_DISABLED_BITS (0 << 1) #define TICKINT_DISABLED_BITS (0U << 1)
#define TICKINT_ENABLED_BITS (1 << 1) #define TICKINT_ENABLED_BITS (1U << 1)
#define CSR_CLKSOURCE_MASK (0x1 << 2) #define CSR_CLKSOURCE_MASK (0x1U << 2)
#define CLKSOURCE_EXT_BITS (0 << 2) #define CLKSOURCE_EXT_BITS (0U << 2)
#define CLKSOURCE_CORE_BITS (1 << 2) #define CLKSOURCE_CORE_BITS (1U << 2)
#define CSR_COUNTFLAG_MASK (0x1 << 16) #define CSR_COUNTFLAG_MASK (0x1U << 16)
#define RVR_RELOAD_MASK (0xFFFFFF << 0) #define RVR_RELOAD_MASK (0xFFFFFFU << 0)
#define CVR_CURRENT_MASK (0xFFFFFF << 0) #define CVR_CURRENT_MASK (0xFFFFFFU << 0)
#define CBVR_TENMS_MASK (0xFFFFFF << 0) #define CBVR_TENMS_MASK (0xFFFFFFU << 0)
#define CBVR_SKEW_MASK (0x1 << 30) #define CBVR_SKEW_MASK (0x1U << 30)
#define CBVR_NOREF_MASK (0x1 << 31) #define CBVR_NOREF_MASK (0x1U << 31)
/** /**
* @brief Structure representing the NVIC I/O space. * @brief Structure representing the NVIC I/O space.
@ -113,7 +115,7 @@ typedef struct {
/** /**
* @brief NVIC peripheral base address. * @brief NVIC peripheral base address.
*/ */
#define NVICBase ((CMx_NVIC *)0xE000E100) #define NVICBase ((CMx_NVIC *)0xE000E100U)
#define NVIC_ISER(n) (NVICBase->ISER[n]) #define NVIC_ISER(n) (NVICBase->ISER[n])
#define NVIC_ICER(n) (NVICBase->ICER[n]) #define NVIC_ICER(n) (NVICBase->ICER[n])
#define NVIC_ISPR(n) (NVICBase->ISPR[n]) #define NVIC_ISPR(n) (NVICBase->ISPR[n])
@ -152,7 +154,7 @@ typedef struct {
/** /**
* @brief SCB peripheral base address. * @brief SCB peripheral base address.
*/ */
#define SCBBase ((CMx_SCB *)0xE000ED00) #define SCBBase ((CMx_SCB *)0xE000ED00U)
#define SCB_CPUID (SCBBase->CPUID) #define SCB_CPUID (SCBBase->CPUID)
#define SCB_ICSR (SCBBase->ICSR) #define SCB_ICSR (SCBBase->ICSR)
#define SCB_VTOR (SCBBase->VTOR) #define SCB_VTOR (SCBBase->VTOR)
@ -174,20 +176,20 @@ typedef struct {
#define SCB_SAR(n) (SCBBase->SAR[n]) #define SCB_SAR(n) (SCBBase->SAR[n])
#define SCB_CPACR (SCBBase->CPACR) #define SCB_CPACR (SCBBase->CPACR)
#define ICSR_VECTACTIVE_MASK (0x1FF << 0) #define ICSR_VECTACTIVE_MASK (0x1FFU << 0)
#define ICSR_RETTOBASE (0x1 << 11) #define ICSR_RETTOBASE (0x1U << 11)
#define ICSR_VECTPENDING_MASK (0x1FF << 12) #define ICSR_VECTPENDING_MASK (0x1FFU << 12)
#define ICSR_ISRPENDING (0x1 << 22) #define ICSR_ISRPENDING (0x1U << 22)
#define ICSR_ISRPREEMPT (0x1 << 23) #define ICSR_ISRPREEMPT (0x1U << 23)
#define ICSR_PENDSTCLR (0x1 << 25) #define ICSR_PENDSTCLR (0x1U << 25)
#define ICSR_PENDSTSET (0x1 << 26) #define ICSR_PENDSTSET (0x1U << 26)
#define ICSR_PENDSVCLR (0x1 << 27) #define ICSR_PENDSVCLR (0x1U << 27)
#define ICSR_PENDSVSET (0x1 << 28) #define ICSR_PENDSVSET (0x1U << 28)
#define ICSR_NMIPENDSET (0x1U << 31) #define ICSR_NMIPENDSET (0x1U << 31)
#define AIRCR_VECTKEY 0x05FA0000 #define AIRCR_VECTKEY 0x05FA0000U
#define AIRCR_PRIGROUP_MASK (0x7 << 8) #define AIRCR_PRIGROUP_MASK (0x7U << 8)
#define AIRCR_PRIGROUP(n) ((n) << 8) #define AIRCR_PRIGROUP(n) ((n##U) << 8)
typedef struct { typedef struct {
IOREG32 unused1[1]; IOREG32 unused1[1];
@ -201,7 +203,7 @@ typedef struct {
/** /**
* @brief FPU peripheral base address. * @brief FPU peripheral base address.
*/ */
#define FPUBase ((CMx_FPU *)0xE000EF30L) #define FPUBase ((CMx_FPU *)0xE000EF30U)
#define SCB_FPCCR (FPUBase->FPCCR) #define SCB_FPCCR (FPUBase->FPCCR)
#define SCB_FPCAR (FPUBase->FPCAR) #define SCB_FPCAR (FPUBase->FPCAR)
#define SCB_FPDSCR (FPUBase->FPDSCR) #define SCB_FPDSCR (FPUBase->FPDSCR)
@ -221,14 +223,14 @@ typedef struct {
#define FPDSCR_AHP (0x1U << 26) #define FPDSCR_AHP (0x1U << 26)
#define FPDSCR_DN (0x1U << 25) #define FPDSCR_DN (0x1U << 25)
#define FPDSCR_FZ (0x1U << 24) #define FPDSCR_FZ (0x1U << 24)
#define FPDSCR_RMODE(n) ((n) << 22) #define FPDSCR_RMODE(n) ((n##U) << 22)
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
void NVICEnableVector(uint32_t n, uint32_t prio); void nvicEnableVector(uint32_t n, uint32_t prio);
void NVICDisableVector(uint32_t n); void nvicDisableVector(uint32_t n);
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio); void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

3
readme.txt
View File

@ -77,6 +77,9 @@
- FIX: Fixed PWM with TIM1 and TIM8 broken in STM32 HAL (bug 3458947). - FIX: Fixed PWM with TIM1 and TIM8 broken in STM32 HAL (bug 3458947).
- FIX: Fixed SYSCFG clock not started in STM32L1/F4 HALs (bug 3449139). - FIX: Fixed SYSCFG clock not started in STM32L1/F4 HALs (bug 3449139).
- FIX: Fixed wrong definitions in STM32L-Discovery board file (bug 3449076). - FIX: Fixed wrong definitions in STM32L-Discovery board file (bug 3449076).
- NEW: Files nvic.c and nvic.h moved under ./os/ports/common/ARMCMx, removed
the duplicated instances under the GCC, IAR and Keil ports. Function names
prefixes changed from "NVIC" to "nvic" because style conventions.
- NEW: Modified the STM32F4-Discovery demo to put critical kernel data - NEW: Modified the STM32F4-Discovery demo to put critical kernel data
structures and stacks in the CCM RAM instead normal RAM. It is done using structures and stacks in the CCM RAM instead normal RAM. It is done using
a special .ld file that can be customized to decide how to allocate data a special .ld file that can be customized to decide how to allocate data