diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
index cea0ae14e..2ba3ded4c 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -461,6 +461,9 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
 
     /* Resetting flash ACR settings to the default value.*/
     FLASH->ACR = 0x00040600U;
+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != 0U) {
+      /* Waiting for flash wait states setup.*/
+    }
 
     /* Resetting all other clock sources and PLLs.*/
     RCC->CRRCR = 0U;
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index a3412d366..b7855fc65 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -537,6 +537,9 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
 
     /* Resetting flash ACR settings to the default value.*/
     FLASH->ACR = 0x00000600U;
+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != 0U) {
+      /* Waiting for flash wait states setup.*/
+    }
 
     /* Resetting all other clock sources and PLLs.*/
     RCC->CRRCR = 0U;