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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5871 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
pcirillo 2013-06-22 16:45:14 +00:00
parent cd5e9f0787
commit 34d1df589e
11 changed files with 19 additions and 54 deletions
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4
os/hal/platforms/SPC560BCxx/spc560bc_registry.h
View File

@ -123,7 +123,7 @@
#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
SPC5_EMIOS0_GLOBAL_PRESCALER)
SPC5_EMIOS0_GPRE_VALUE)
#define SPC5_HAS_EMIOS1 TRUE
@ -159,7 +159,7 @@
#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
SPC5_EMIOS1_GLOBAL_PRESCALER)
SPC5_EMIOS1_GPRE_VALUE)
/* FlexCAN attributes.*/
#define SPC5_HAS_FLEXCAN0 TRUE

2
os/hal/platforms/SPC563Mxx/spc563m_registry.h
View File

@ -121,7 +121,7 @@
#define SPC5_EMIOS_FLAG_F23_NUMBER 209
#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \
SPC5_EMIOS_GLOBAL_PRESCALER)
SPC5_EMIOS_GPRE_VALUE)
#define SPC5_EMIOS_ENABLE_CLOCK()
#define SPC5_EMIOS_DISABLE_CLOCK()
/** @} */

2
os/hal/platforms/SPC564Axx/spc564a_registry.h
View File

@ -162,7 +162,7 @@
#define SPC5_EMIOS_FLAG_F23_NUMBER 209
#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \
SPC5_EMIOS_GLOBAL_PRESCALER)
SPC5_EMIOS_GPRE_VALUE)
#define SPC5_EMIOS_ENABLE_CLOCK()
#define SPC5_EMIOS_DISABLE_CLOCK()
/** @} */

4
os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
View File

@ -74,7 +74,7 @@ void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
/* Disable all unified channels.*/
if (icup != NULL) {
icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
@ -83,7 +83,7 @@ void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
} else if (pwmp != NULL) {
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;

30
os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
View File

@ -161,7 +161,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
_icu_isr_invoke_overflow_cb(icup);
}
if (sr && EMIOSS_FLAG){
if (sr && EMIOSS_FLAG) {
icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
@ -191,7 +191,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
}
}
}
if(sr && EMIOSS_OVR){
if (sr && EMIOSS_OVR) {
icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
}
@ -489,9 +489,6 @@ void icu_lld_init(void) {
*/
void icu_lld_start(ICUDriver *icup) {
//uint32_t emios0_active_channels = get_emios0_active_channels();
//uint32_t emios1_active_channels = get_emios1_active_channels();
chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
"too many channels");
@ -568,23 +565,12 @@ void icu_lld_start(ICUDriver *icup) {
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"icu_lld_start(), #1", "invalid frequency");
//icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
icup->emiosp->CH[icup->ch_number].CCR.R |=
EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
/*
if (icup->emiosp == &EMIOS_0) {
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
} else if (icup->emiosp == &EMIOS_1) {
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
}
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
*/
/* Set source polarity.*/
if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
@ -612,9 +598,6 @@ void icu_lld_start(ICUDriver *icup) {
*/
void icu_lld_stop(ICUDriver *icup) {
//uint32_t emios0_active_channels = get_emios0_active_channels();
//uint32_t emios1_active_channels = get_emios1_active_channels();
chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
"too many channels");
chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
@ -746,15 +729,6 @@ void icu_lld_enable(ICUDriver *icup) {
icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
}
/* Enable Global Time Base.*/
/*
if (icup->emiosp->MCR.B.GTBE == 0) {
icup->emiosp->MCR.B.GTBE = 1U;
}
*/
}
/**

12
os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
View File

@ -92,7 +92,7 @@ void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
/* Disable all unified channels.*/
if (icup != NULL) {
icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
@ -101,7 +101,7 @@ void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
} else if (pwmp != NULL) {
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
@ -122,7 +122,7 @@ void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
/* Disable all unified channels.*/
if (icup != NULL) {
icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
@ -131,7 +131,7 @@ void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
} else if (pwmp != NULL) {
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
@ -148,13 +148,11 @@ void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
if (emios0_active_channels == 0) {
if (icup != NULL) {
if (icup->emiosp->UCDIS.R == 0) {
//icup->emiosp->MCR.B.MDIS = 0;
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
} else if (pwmp != NULL) {
if (pwmp->emiosp->UCDIS.R == 0) {
//pwmp->emiosp->MCR.B.MDIS = 0;
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
@ -167,13 +165,11 @@ void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
if (emios1_active_channels == 0) {
if (icup != NULL) {
if (icup->emiosp->UCDIS.R == 0) {
//icup->emiosp->MCR.B.MDIS = 0;
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_STOP_PCTL);
}
} else if (pwmp != NULL) {
if (pwmp->emiosp->UCDIS.R == 0) {
//pwmp->emiosp->MCR.B.MDIS = 0;
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_STOP_PCTL);
}

7
testhal/SPC560BCxx/ICU-PWM/mcuconf.h
View File

@ -161,6 +161,9 @@
#define SPC5_PIT0_IRQ_PRIORITY 4
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
#define SPC5_EMIOS0_GPRE_VALUE 200
#define SPC5_EMIOS1_GPRE_VALUE 200
/*
* SERIAL driver system settings.
*/
@ -180,8 +183,6 @@
/*
* ICU-PWM driver system settings.
*/
#define SPC5_EMIOS0_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
#define SPC5_ICU_USE_EMIOS0_CH0 TRUE
#define SPC5_ICU_USE_EMIOS0_CH1 TRUE
#define SPC5_ICU_USE_EMIOS0_CH2 TRUE
@ -214,8 +215,6 @@
#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_EMIOS1_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
#define SPC5_ICU_USE_EMIOS1_CH24 TRUE
#define SPC5_PWM_USE_EMIOS1_GROUP0 TRUE

2
testhal/SPC563Mxx/ICU-PWM/.cproject
View File

@ -39,7 +39,7 @@
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="SPC563Mxx-SPI.null.1461388361" name="SPC563Mxx-SPI"/>
<project id="SPC563Mxx-ICU-PWM.null.1461388361" name="SPC563Mxx-ICU-PWM"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>

2
testhal/SPC563Mxx/ICU-PWM/.project
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>SPC563Mxx-SPI</name>
<name>SPC563Mxx-ICU-PWM</name>
<comment></comment>
<projects>
</projects>

4
testhal/SPC563Mxx/ICU-PWM/mcuconf.h
View File

@ -43,7 +43,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
#define SPC5_EMIOS_GPRE_VALUE 200
/*
* ADC driver settings.
@ -97,5 +97,3 @@
#define SPC5_PWM_USE_EMIOS_CH14 TRUE
#define SPC5_PWM_USE_EMIOS_CH15 TRUE
#define SPC5_PWM_USE_EMIOS_CH23 TRUE
#define SPC5_EMIOS_GLOBAL_PRESCALER 200

4
testhal/SPC564Axx/ICU-PWM/mcuconf.h
View File

@ -43,7 +43,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
#define SPC5_EMIOS_GPRE_VALUE 200
/*
* ADC driver settings.
@ -105,5 +105,3 @@
#define SPC5_PWM_USE_EMIOS_CH21 TRUE
#define SPC5_PWM_USE_EMIOS_CH22 TRUE
#define SPC5_PWM_USE_EMIOS_CH23 TRUE
#define SPC5_EMIOS_GLOBAL_PRESCALER 200