Updated STM32L0xx CMSIS headers

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9404 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-05-02 20:37:31 +00:00
parent ac22f03ce3
commit 359690b63c
18 changed files with 57547 additions and 14663 deletions

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.1.0
* @date 18-June-2014
* @version V1.5.0
* @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +20,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -66,18 +66,39 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32L0)
#define STM32L0
#endif /* STM32L0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \
!defined (STM32L063xx) && !defined (STM32L061xx)
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */
#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
!defined (STM32L031xx) && !defined (STM32L041xx) && \
!defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
!defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
!defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
!defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
/* #define STM32L011xx */
/* #define STM32L021xx */
/* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L061xx */
/* #define STM32L071xx */ /*!< */
/* #define STM32L072xx */ /*!< */
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
/* #define STM32L081xx */ /*!< */
/* #define STM32L082xx */ /*!< */
/* #define STM32L083xx */ /*!< */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -93,16 +114,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.0
* @brief CMSIS Device version number V1.5.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION))
/**
* @}
@ -111,8 +132,15 @@
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32L051xx)
#if defined(STM32L011xx)
#include "stm32l011xx.h"
#elif defined(STM32L021xx)
#include "stm32l021xx.h"
#elif defined(STM32L031xx)
#include "stm32l031xx.h"
#elif defined(STM32L041xx)
#include "stm32l041xx.h"
#elif defined(STM32L051xx)
#include "stm32l051xx.h"
#elif defined(STM32L052xx)
#include "stm32l052xx.h"
@ -124,6 +152,18 @@
#include "stm32l063xx.h"
#elif defined(STM32L061xx)
#include "stm32l061xx.h"
#elif defined(STM32L071xx)
#include "stm32l071xx.h"
#elif defined(STM32L072xx)
#include "stm32l072xx.h"
#elif defined(STM32L073xx)
#include "stm32l073xx.h"
#elif defined(STM32L082xx)
#include "stm32l082xx.h"
#elif defined(STM32L083xx)
#include "stm32l083xx.h"
#elif defined(STM32L081xx)
#include "stm32l081xx.h"
#else
#error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
#endif
@ -176,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
*/
@ -186,7 +224,6 @@ typedef enum
#include "stm32l0xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.1.0
* @date 18-June-2014
* @version V1.5.0
* @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}