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Fixed wrong USART 2 configuration in STM32 Nucleo32 L011K4 boards file 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9417 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-05-05 08:25:04 +00:00
parent 2ceb952a73
commit 35db3cabce
2 changed files with 6 additions and 6 deletions
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8
os/hal/boards/ST_NUCLEO32_L011K4/board.h
View File

@ -219,7 +219,7 @@
*
* PA0 - ARD_A0 (input pullup).
* PA1 - ARD_A1 (input pullup).
* PA2 - VCP_TX (alternate 1).
* PA2 - VCP_TX (alternate 4).
* PA3 - ARD_A2 (input pullup).
* PA4 - ARD_A3 (input pullup).
* PA5 - ARD_A4 (input pullup).
@ -232,7 +232,7 @@
* PA12 - ARD_D2 (input pullup).
* PA13 - SWDIO (alternate 0).
* PA14 - SWCLK (alternate 0).
* PA15 - VCP_RX (alternate 1).
* PA15 - VCP_RX (alternate 4).
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \
PIN_MODE_INPUT(GPIOA_ARD_A1) | \
@ -316,7 +316,7 @@
PIN_ODR_HIGH(GPIOA_VCP_RX))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A1, 0) | \
PIN_AFIO_AF(GPIOA_VCP_TX, 1) | \
PIN_AFIO_AF(GPIOA_VCP_TX, 4) | \
PIN_AFIO_AF(GPIOA_ARD_A2, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A3, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A4, 0) | \
@ -329,7 +329,7 @@
PIN_AFIO_AF(GPIOA_ARD_D2, 0) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_VCP_RX, 1))
PIN_AFIO_AF(GPIOA_VCP_RX, 4))
/*
* GPIOB setup:

4
os/hal/boards/ST_NUCLEO32_L011K4/cfg/board.chcfg
View File

@ -39,7 +39,7 @@
Speed="High"
Resistor="Floating"
Mode="Alternate"
Alternate="1" />
Alternate="4" />
<pin3
ID="ARD_A2"
Type="PushPull"
@ -143,7 +143,7 @@
Speed="Maximum"
Resistor="Floating"
Mode="Alternate"
Alternate="1" />
Alternate="4" />
</GPIOA>
<GPIOB>
<pin0