git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@69 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -64,6 +64,7 @@ UADEFS =
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# List ARM-mode C source files here
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# List ARM-mode C source files here
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ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \
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ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \
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../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \
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../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \
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../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \
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../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \
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../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \
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../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \
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../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \
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../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c
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../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c
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@ -22,6 +22,7 @@
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#include "lpc214x.h"
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#include "lpc214x.h"
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#include "vic.h"
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#include "vic.h"
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#include "lpc214x_serial.h"
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#include "lpc214x_serial.h"
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#include "lpc214x_ssp.h"
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#include "buzzer.h"
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#include "buzzer.h"
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@ -117,6 +118,7 @@ void hwinit(void) {
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SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
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SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
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SetVICVector(UART0IrqHandler, 1, SOURCE_UART0);
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SetVICVector(UART0IrqHandler, 1, SOURCE_UART0);
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SetVICVector(UART1IrqHandler, 2, SOURCE_UART1);
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SetVICVector(UART1IrqHandler, 2, SOURCE_UART1);
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SetVICVector(SSPIrqHandler, 3, SOURCE_SPI1);
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/*
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/*
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* System Timer initialization, 1ms intervals.
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* System Timer initialization, 1ms intervals.
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@ -133,6 +135,7 @@ void hwinit(void) {
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* Other subsystems.
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* Other subsystems.
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*/
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*/
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InitSerial();
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InitSerial();
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InitSSP();
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InitBuzzer();
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InitBuzzer();
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}
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}
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@ -155,6 +155,16 @@ UART1IrqHandler:
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bl UART1Irq
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bl UART1Irq
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b IrqCommon
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b IrqCommon
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.globl SSPIrqHandler
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SSPIrqHandler:
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sub lr, lr, #4
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stmfd sp!, {r0-r3, r12, lr}
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mrs r0, SPSR // Workaround for ARM7TDMI+VIC
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tst r0, #I_BIT // spurious interrupts.
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ldmnefd sp!, {r0-r3, r12, pc}^
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bl SSPIrq
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b IrqCommon
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/*
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/*
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* Common exit point for all IRQ routines, it performs the rescheduling if
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* Common exit point for all IRQ routines, it performs the rescheduling if
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* required.
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* required.
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@ -337,6 +337,81 @@ typedef struct {
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#define TER_ENABLE 0x80
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#define TER_ENABLE 0x80
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/*
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* SSP.
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*/
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typedef struct {
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IOREG32 SSP_CR0;
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IOREG32 SSP_CR1;
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IOREG32 SSP_DR;
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IOREG32 SSP_SR;
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IOREG32 SSP_CPSR;
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IOREG32 SSP_IMSC;
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IOREG32 SSP_RIS;
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IOREG32 SSP_MIS;
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IOREG32 SSP_ICR;
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} SSP;
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#define SSPBase ((SSP *)0xE0068000)
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#define SSPCR0 (SSPBase->SSP_CR0)
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#define SSPCR1 (SSPBase->SSP_CR1)
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#define SSPDR (SSPBase->SSP_DR)
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#define SSPSR (SSPBase->SSP_SR)
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#define SSPCPSR (SSPBase->SSP_CPSR)
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#define SSPIMSC (SSPBase->SSP_IMSC)
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#define SSPRIS (SSPBase->SSP_RIS)
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#define SSPMIS (SSPBase->SSP_MIS)
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#define SSPICR (SSPBase->SSP_ICR)
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#define CR0_DSS4BIT 3
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#define CR0_DSS5BIT 4
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#define CR0_DSS6BIT 5
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#define CR0_DSS7BIT 6
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#define CR0_DSS8BIT 7
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#define CR0_DSS9BIT 8
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#define CR0_DSS10BIT 9
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#define CR0_DSS11BIT 0xA
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#define CR0_DSS12BIT 0xB
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#define CR0_DSS13BIT 0xC
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#define CR0_DSS14BIT 0xD
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#define CR0_DSS15BIT 0xE
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#define CR0_DSS16BIT 0xF
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#define CR0_FRFSPI 0
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#define CR0_FRFSSI 0x10
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#define CR0_FRFMW 0x20
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#define CR0_CPOL 0x40
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#define CR0_CPHA 0x80
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#define CR0_CLOCKRATE(n) ((n) << 8)
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#define CR1_LBM 1
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#define CR1_SSE 2
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#define CR1_MS 4
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#define CR1_SOD 8
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#define SR_TFE 1
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#define SR_TNF 2
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#define SR_RNE 4
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#define SR_RFF 8
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#define SR_BSY 0x10
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#define IMSC_ROR 1
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#define IMSC_RT 2
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#define IMSC_RX 4
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#define IMSC_TX 8
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#define RIS_ROR 1
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#define RIS_RT 2
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#define RIS_RX 4
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#define RIS_TX 8
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#define MIS_ROR 1
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#define MIS_RT 2
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#define MIS_RX 4
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#define MIS_TX 8
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#define ICR_ROR 1
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#define ICR_RT 2
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/*
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/*
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* Timers/Counters.
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* Timers/Counters.
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*/
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*/
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@ -0,0 +1,78 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include "lpc214x.h"
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#include "lpc214x_ssp.h"
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static BYTE8 *ip, *op;
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static t_size icnt, ocnt;
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static t_sspnotify callback;
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void SSPIrq(void) {
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}
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/*
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* Starts an asynchronous SSP transfer.
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* @param in pointer to the incoming data buffer, if this parameter is set to
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* \p NULL then the incoming data is discarded.
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* @param out pointer to the outgoing data buffer, if this parameter is set to
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* \p NULL then 0xFF bytes will be output.
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* @param n the number of bytes to be transferred
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* @param fn callback function invoked when the operation is done
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* @return \p SSP_OK if the trasfer is started else \p SSP_RUNNING if a
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* an operation was already started
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*/
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t_msg sspRWI(BYTE8 *in, BYTE8 *out, t_size n, t_sspnotify fn) {
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if (callback)
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return SSP_RUNNING;
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callback = fn, ip = in, op = out, icnt = ocnt = n;
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SSPIMSC = IMSC_ROR | IMSC_RT | IMSC_RX | IMSC_TX;
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return SSP_OK;
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}
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/*
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* SSP setup, must be invoked with interrupts disabled.
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* Do not invoke while an operation is in progress.
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*/
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void SetSSPI(int cpsr, int cr0, int cr1) {
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SSP *ssp = SSPBase;
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ssp->SSP_CR1 = cr1 & ~CR1_SSE;
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ssp->SSP_CR0 = cr0;
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ssp->SSP_CPSR = cpsr;
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ssp->SSP_CR1 = cr1 | CR1_SSE;
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}
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/*
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* SSP subsystem initialization.
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*/
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void InitSSP(void) {
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/* Enables the SPI1 clock */
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PCONP = (PCONP & PCALL) | PCSPI1;
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/* Clock = PCLK / 2 */
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SetSSPI(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0);
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VICIntEnable = INTMASK(SOURCE_SPI1);
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}
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@ -0,0 +1,32 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _LPC214x_SSP_H_
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#define _LPC214x_SSP_H_
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#define SSP_OK RDY_OK
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#define SSP_RUNNING -3
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typedef void (*t_sspnotify)(void);
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void InitSSP(void);
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void SetSSPI(int cpsr, int cr0, int cr1);
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void SSPIrqHandler(void);
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#endif /* _LPC214x_SSP_H_*/
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@ -38,6 +38,9 @@ AVR-AT90CANx-GCC - Port on AVR AT90CAN128, not complete yet.
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*** Releases ***
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*** Releases ***
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*****************************************************************************
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*****************************************************************************
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*** 0.3.6 ***
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- Added SSP (SPI1) definitions to the lpc214x.h file.
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*** 0.3.5 ***
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*** 0.3.5 ***
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- Space optimization in events code.
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- Space optimization in events code.
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- Changed the behavior of chEvtWaitTimeout() when the timeout parameter is
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- Changed the behavior of chEvtWaitTimeout() when the timeout parameter is
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