Modified the STM32F4xx HSI (re)activation, removed redundant |=
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6433 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -158,11 +158,15 @@ void stm32_clock_init(void) {
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PWR->CR = 0;
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#endif
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/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
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always enabled because it is the fallback clock when PLL the fails.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Waits until HSI is stable. */
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Waits until HSI is selected. */
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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@ -223,7 +227,7 @@ void stm32_clock_init(void) {
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#endif
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
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RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
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STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup.*/
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