git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1913 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
302956a3d9
commit
36cc348d07
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@ -18,8 +18,9 @@
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*/
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*/
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/**
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/**
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* @file STM32/hal_lld.c
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* @file STM32/hal_lld.c
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* @brief STM32 HAL subsystem low level driver source.
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* @brief STM32 HAL subsystem low level driver source.
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*
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* @addtogroup STM32_HAL
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* @addtogroup STM32_HAL
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* @{
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* @{
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*/
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*/
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@ -18,8 +18,9 @@
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*/
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*/
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/**
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/**
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* @file STM32/hal_lld.h
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* @file STM32/hal_lld.h
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* @brief STM32 HAL subsystem low level driver header.
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* @brief STM32 HAL subsystem low level driver header.
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*
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* @addtogroup STM32_HAL
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* @addtogroup STM32_HAL
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* @{
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* @{
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*/
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*/
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@ -38,300 +39,25 @@
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#include "nvic.h"
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#include "nvic.h"
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#include "stm32_dma.h"
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#include "stm32_dma.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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/**
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* @brief Platform name.
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* @brief Platform name.
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*/
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*/
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#if defined(STM32F10X_LD)
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#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32 LD"
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#elif defined(STM32F10X_MD)
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#define PLATFORM_NAME "STM32 MD"
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#define PLATFORM_NAME "STM32 MD"
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#include "hal_lld_F10x.h"
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#elif defined(STM32F10X_LD)
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#define PLATFORM_NAME "STM32 LD"
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#include "hal_lld_F10x.h"
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#elif defined(STM32F10X_HD)
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#elif defined(STM32F10X_HD)
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#define PLATFORM_NAME "STM32 HD"
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#define PLATFORM_NAME "STM32 HD"
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#include "hal_lld_F10x.h"
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#elif defined(STM32F10X_CL)
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#elif defined(STM32F10X_CL)
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#define PLATFORM_NAME "STM32 CL"
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#define PLATFORM_NAME "STM32 CL"
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#include "hal_lld_F107.h"
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#else
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#else
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#define PLATFORM_NAME "STM32"
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#error "STM32 platform not specified"
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#endif
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#endif
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#define STM32_HSICLK 8000000 /**< High speed internal clock. */
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#define STM32_LSICLK 40000 /**< Low speed internal clock. */
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#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
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#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
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#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
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#define STM32_ADCPRE_DIV9 (3 << 14) /**< HCLK divided by 8. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
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#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL the the PLL is not
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* initialized and started.
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*/
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#define STM32_SW STM32_SW_PLL
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/**
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#endif
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/**
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* @brief Crystal PLL pre-divider.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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*/
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#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#endif
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/**
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* @brief Desired PLL output frequency.
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* @note The PLL multiplier is calculated from the input clock and this
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* value.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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*/
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#if !defined(STM32_PLLCLKOUT) || defined(__DOXYGEN__)
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#define STM32_PLLCLKOUT 72000000
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#endif
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/**
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* @brief AHB prescaler value.
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* @note It is recommended to not change this default.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_HPRE STM32_HPRE_DIV1
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#endif
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/**
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* @brief APB1 prescaler value.
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* @note It is recommended to not change this default.
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*/
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#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#endif
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/**
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* @brief APB2 prescaler value.
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* @note It is recommended to not change this default.
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*/
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#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#endif
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/**
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* @brief ADC prescaler value.
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* @note It is recommended to not change this default.
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*/
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#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADCPRE STM32_ADCPRE_DIV2
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
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(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
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#error "invalid STM32_PLLXTPRE value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#else
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#define STM32_PLLCLKIN (STM32_HSECLK / 2)
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#endif
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/**
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* @brief PLL multiplier.
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*/
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#define STM32_PLLMUL (STM32_PLLCLKOUT / STM32_PLLCLKIN)
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#if (STM32_PLLMUL % 1) != 0
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#error "the requested PLL output frequency is not a multiple of the input frequency"
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#endif
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#if (STM32_PLLMUL < 2) || (STM32_PLLMUL > 16)
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#error "the calculated PLL multiplier is out of the allowed range (2...16)"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#define STM32_PLLCLK (STM32_PLLCLKIN * STM32_PLLMUL)
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/**
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* @brief System clock source.
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*/
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#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
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#define STM32_SYSCLK STM32_PLLCLK
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#elif (STM32_SW == STM32_SW_HSI)
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#define STM32_SYSCLK STM32_HSICLK
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#elif (STM32_SW == STM32_SW_HSE)
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#define STM32_SYSCLK STM32_HSECLK
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#else
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#error "invalid STM32_SYSCLK_SW value specified"
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#endif
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#if STM32_SYSCLK > 72000000
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#error "STM32_SYSCLK above maximum rated frequency (72MHz)"
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#endif
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/**
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* @brief AHB frequency.
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*/
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#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#elif STM32_HPRE == STM32_HPRE_DIV2
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#define STM32_HCLK (STM32_SYSCLK / 2)
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#elif STM32_HPRE == STM32_HPRE_DIV4
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#define STM32_HCLK (STM32_SYSCLK / 4)
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#elif STM32_HPRE == STM32_HPRE_DIV8
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#define STM32_HCLK (STM32_SYSCLK / 8)
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#elif STM32_HPRE == STM32_HPRE_DIV16
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#define STM32_HCLK (STM32_SYSCLK / 16)
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#elif STM32_HPRE == STM32_HPRE_DIV64
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#define STM32_HCLK (STM32_SYSCLK / 64)
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#elif STM32_HPRE == STM32_HPRE_DIV128
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#define STM32_HCLK (STM32_SYSCLK / 128)
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#elif STM32_HPRE == STM32_HPRE_DIV256
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#define STM32_HCLK (STM32_SYSCLK / 256)
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#elif STM32_HPRE == STM32_HPRE_DIV512
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#define STM32_HCLK (STM32_SYSCLK / 512)
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#else
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#error "invalid STM32_HPRE value specified"
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#endif
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#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK1 (STM32_HCLK / 1)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV2
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#define STM32_PCLK1 (STM32_HCLK / 2)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV4
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#define STM32_PCLK1 (STM32_HCLK / 4)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV8
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#define STM32_PCLK1 (STM32_HCLK / 8)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV16
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#define STM32_PCLK1 (STM32_HCLK / 16)
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#else
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#error "invalid STM32_PPRE1 value specified"
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#endif
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#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK2 (STM32_HCLK / 1)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV2
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#define STM32_PCLK2 (STM32_HCLK / 2)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV4
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#define STM32_PCLK2 (STM32_HCLK / 4)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV8
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#define STM32_PCLK2 (STM32_HCLK / 8)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV16
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#define STM32_PCLK2 (STM32_HCLK / 16)
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#else
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#error "invalid STM32_PPRE2 value specified"
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#endif
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/**
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* @brief Flash settings.
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*/
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#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
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#define STM32_FLASHBITS 0x00000010
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#elif STM32_HCLK <= 48000000
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#define STM32_FLASHBITS 0x00000011
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#else
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#define STM32_FLASHBITS 0x00000012
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#endif
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#if 0
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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*/
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#define PLLPRE 1
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#if STM32_SYSCLK == 48
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#define PLLMUL 6
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#elif STM32_SYSCLK == 72
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#define PLLMUL 9
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#else
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#define PLLMUL 555
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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#define TIMCLK2 (APB2CLK * 2)
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#define TIMCLK1 (APB1CLK * 2)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#if STM32_SYSCLK == 48
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#define USBPREBITS RCC_CFGR_USBPRE
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#define FLASHBITS 0x00000011
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#elif STM32_SYSCLK == 72
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#define USBPREBITS 0
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#define FLASHBITS 0x00000012
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#endif
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/* External declarations. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -0,0 +1,274 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
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it under the terms of the GNU General Public License as published by
|
||||||
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the Free Software Foundation; either version 3 of the License, or
|
||||||
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(at your option) any later version.
|
||||||
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|
||||||
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ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32/hal_lld_F10x.h
|
||||||
|
* @brief STM32F10x HAL subsystem low level driver header.
|
||||||
|
*
|
||||||
|
* @addtogroup STM32F10x_HAL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _HAL_LLD_F10X_H_
|
||||||
|
#define _HAL_LLD_F10X_H_
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
|
||||||
|
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
|
||||||
|
|
||||||
|
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||||
|
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||||
|
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
|
||||||
|
|
||||||
|
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
|
||||||
|
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
|
||||||
|
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
|
||||||
|
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
|
||||||
|
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
|
||||||
|
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
|
||||||
|
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
|
||||||
|
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
|
||||||
|
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
|
||||||
|
|
||||||
|
#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
|
||||||
|
#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
|
||||||
|
#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
|
||||||
|
#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
|
||||||
|
#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
|
||||||
|
|
||||||
|
#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
|
||||||
|
#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
|
||||||
|
#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
|
||||||
|
#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
|
||||||
|
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
|
||||||
|
|
||||||
|
#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
|
||||||
|
#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
|
||||||
|
#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
|
||||||
|
#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
|
||||||
|
|
||||||
|
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
|
||||||
|
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
|
||||||
|
|
||||||
|
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
|
||||||
|
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Main clock source selection.
|
||||||
|
* @note If the selected clock source is not the PLL the the PLL is not
|
||||||
|
* initialized and started.
|
||||||
|
*/
|
||||||
|
#define STM32_SW STM32_SW_PLL
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clock source for the PLL.
|
||||||
|
* @note This setting has only effect if the PLL is selected as the
|
||||||
|
* system clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Crystal PLL pre-divider.
|
||||||
|
* @note This setting has only effect if the PLL is selected as the
|
||||||
|
* system clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Desired PLL output frequency.
|
||||||
|
* @note The PLL multiplier is calculated from the input clock and this
|
||||||
|
* value.
|
||||||
|
* @note This setting has only effect if the PLL is selected as the
|
||||||
|
* system clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLLCLKOUT) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLLCLKOUT 72000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief AHB prescaler value.
|
||||||
|
* @note It is recommended to not change this default.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_HPRE STM32_HPRE_DIV1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief APB1 prescaler value.
|
||||||
|
* @note It is recommended to not change this default.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief APB2 prescaler value.
|
||||||
|
* @note It is recommended to not change this default.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC prescaler value.
|
||||||
|
* @note It is recommended to not change this default.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_ADCPRE STM32_ADCPRE_DIV2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/* HSE prescaler setting check.*/
|
||||||
|
#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
|
||||||
|
(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
|
||||||
|
#error "invalid STM32_PLLXTPRE value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ADC prescaler setting check.*/
|
||||||
|
#if (STM32_ADCPRE != STM32_PLLXTPRE_DIV2) && \
|
||||||
|
(STM32_ADCPRE != STM32_PLLXTPRE_DIV4) && \
|
||||||
|
(STM32_ADCPRE != STM32_PLLXTPRE_DIV6) && \
|
||||||
|
(STM32_ADCPRE != STM32_PLLXTPRE_DIV8)
|
||||||
|
#error "invalid STM32_ADCPRE value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL input clock frequency.
|
||||||
|
*/
|
||||||
|
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||||
|
#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
|
||||||
|
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||||
|
#else
|
||||||
|
#define STM32_PLLCLKIN (STM32_HSECLK / 2)
|
||||||
|
#endif
|
||||||
|
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||||
|
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||||
|
#else
|
||||||
|
#error "invalid STM32_PLLSRC value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL multiplier.
|
||||||
|
*/
|
||||||
|
#define STM32_PLLMUL (STM32_PLLCLKOUT / STM32_PLLCLKIN)
|
||||||
|
#if (STM32_PLLMUL % 1) != 0
|
||||||
|
#error "the requested PLL output frequency is not a multiple of the input frequency"
|
||||||
|
#endif
|
||||||
|
#if (STM32_PLLMUL < 2) || (STM32_PLLMUL > 16)
|
||||||
|
#error "the calculated PLL multiplier is out of the allowed range (2...16)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System clock source.
|
||||||
|
*/
|
||||||
|
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||||
|
#elif (STM32_SW == STM32_SW_HSI)
|
||||||
|
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||||
|
#elif (STM32_SW == STM32_SW_HSE)
|
||||||
|
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||||
|
#else
|
||||||
|
#error "invalid STM32_SYSCLK_SW value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SYSCLK > 72000000
|
||||||
|
#error "STM32_SYSCLK above maximum rated frequency (72MHz)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief AHB frequency.
|
||||||
|
*/
|
||||||
|
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV2
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 2)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV4
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 4)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV8
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 8)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV16
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 16)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV64
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 64)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV128
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 128)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV256
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 256)
|
||||||
|
#elif STM32_HPRE == STM32_HPRE_DIV512
|
||||||
|
#define STM32_HCLK (STM32_SYSCLK / 512)
|
||||||
|
#else
|
||||||
|
#error "invalid STM32_HPRE value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PCLK1 (STM32_HCLK / 1)
|
||||||
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
||||||
|
#define STM32_PCLK1 (STM32_HCLK / 2)
|
||||||
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
||||||
|
#define STM32_PCLK1 (STM32_HCLK / 4)
|
||||||
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
||||||
|
#define STM32_PCLK1 (STM32_HCLK / 8)
|
||||||
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
||||||
|
#define STM32_PCLK1 (STM32_HCLK / 16)
|
||||||
|
#else
|
||||||
|
#error "invalid STM32_PPRE1 value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PCLK2 (STM32_HCLK / 1)
|
||||||
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
||||||
|
#define STM32_PCLK2 (STM32_HCLK / 2)
|
||||||
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
||||||
|
#define STM32_PCLK2 (STM32_HCLK / 4)
|
||||||
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
||||||
|
#define STM32_PCLK2 (STM32_HCLK / 8)
|
||||||
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
||||||
|
#define STM32_PCLK2 (STM32_HCLK / 16)
|
||||||
|
#else
|
||||||
|
#error "invalid STM32_PPRE2 value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Flash settings.
|
||||||
|
*/
|
||||||
|
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_FLASHBITS 0x00000010
|
||||||
|
#elif STM32_HCLK <= 48000000
|
||||||
|
#define STM32_FLASHBITS 0x00000011
|
||||||
|
#else
|
||||||
|
#define STM32_FLASHBITS 0x00000012
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _HAL_LLD_F10X_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -40,6 +40,13 @@
|
||||||
* @ingroup STM32
|
* @ingroup STM32
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @defgroup STM32F10x_HAL STM32F103 HAL Support
|
||||||
|
* @brief HAL support for STM32 LD, MD and HD families.
|
||||||
|
*
|
||||||
|
* @ingroup STM32_HAL
|
||||||
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @defgroup STM32_PAL STM32 I/O Ports Support
|
* @defgroup STM32_PAL STM32 I/O Ports Support
|
||||||
* @brief I/O Ports peripherals support.
|
* @brief I/O Ports peripherals support.
|
||||||
|
|
|
||||||
|
|
@ -61,6 +61,9 @@
|
||||||
*** 1.5.7 ***
|
*** 1.5.7 ***
|
||||||
- NEW: Improved clock initialization for the STM32, now it is possible to
|
- NEW: Improved clock initialization for the STM32, now it is possible to
|
||||||
configure the clock using any clock source and any HSE frequency.
|
configure the clock using any clock source and any HSE frequency.
|
||||||
|
The clock tree parameters and checks are now calculated into a separate
|
||||||
|
file in order to support multiple clock trees for different families of
|
||||||
|
the STM32 platform.
|
||||||
|
|
||||||
*** 1.5.6 ***
|
*** 1.5.6 ***
|
||||||
- FIX: Fixed centralized ARM makefile (bug 2992747)(backported in 1.4.3).
|
- FIX: Fixed centralized ARM makefile (bug 2992747)(backported in 1.4.3).
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue