andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1771 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-03-22 13:39:26 +00:00
parent e72ad7fd5f
commit 36f96c9fef
17 changed files with 130 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
demos/ARMCM3-STM32F103-FATFS-GCC/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
include $(CHIBIOS)/ext/fatfs/fatfs.mk
@ -104,7 +104,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
@ -156,7 +156,7 @@ CPPWARN = -Wall -Wextra
#
# List all default C defines here, like -D_DEBUG=1
DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2
DDEFS = -DSTM32F10X_MD -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =

35
demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h
View File

@ -25,10 +25,11 @@
* is enabled in halconf.h.
*
* IRQ priorities:
* 0xF0 Lowest, priority level reserved for PENDSV.
* 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK).
* 0x30 Used by SVCALL, do not share.
* 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it.
* 15 Lowest, priority level reserved for PENDSV.
* 14...4 Normal IRQs priority levels (0x80 used by SYSTICK).
* 3 Used by SVCALL, do not share.
* 2...0 Fast interrupts, can preempt the kernel but cannot use it
* directly.
*
* DMA priorities:
* 0...3 Lowest...Highest.
@ -44,14 +45,14 @@
*/
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
#define STM32_ADC1_IRQ_PRIORITY 0x50
#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
#define STM32_CAN1_IRQ_PRIORITY 0xB0
#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
/*
* PWM driver system settings.
@ -60,10 +61,10 @@
#define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
#define STM32_PWM1_IRQ_PRIORITY 0x70
#define STM32_PWM2_IRQ_PRIORITY 0x70
#define STM32_PWM3_IRQ_PRIORITY 0x70
#define STM32_PWM4_IRQ_PRIORITY 0x70
#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
/*
* SERIAL driver system settings.
@ -75,12 +76,12 @@
#define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
#define STM32_USART1_PRIORITY 0xC0
#define STM32_USART2_PRIORITY 0xC0
#define STM32_USART3_PRIORITY 0xC0
#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#define STM32_UART4_PRIORITY 0xC0
#define STM32_UART5_PRIORITY 0xC0
#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
#endif
/*
@ -90,6 +91,6 @@
#define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
#define STM32_SPI1_IRQ_PRIORITY 0xA0
#define STM32_SPI2_IRQ_PRIORITY 0xA0
#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()

4
demos/ARMCM3-STM32F103-GCC/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
@ -102,7 +102,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \

5
docs/Doxyfile
View File

@ -583,8 +583,9 @@ INPUT = ../docs/src \
../os/ports/GCC/ARM7 \
../os/ports/GCC/ARM7/crt0.s \
../os/ports/GCC/ARM7/chcoreasm.s \
../os/ports/GCC/ARMCM3 \
../os/ports/GCC/ARMCM3/crt0.s \
../os/ports/GCC/ARMCMx \
../os/ports/GCC/ARMCMx/crt0.s \
../os/ports/GCC/ARMCMx\STM32F103 \
../os/ports/GCC/PPC \
../os/ports/GCC/PPC/crt0.s \
../os/ports/GCC/MSP430 \

2
os/hal/platforms/STM32/platform.dox
View File

@ -30,7 +30,7 @@
* - A demo supporting the kernel test suite.
* - A demo that demonstrate the FatFs use with the MMC driver.
* .
* @ingroup ARMCM3
* @ingroup ARMCMx
*/
/**

9
os/ports/GCC/ARMCMx/STM32F103/cmparams.h
View File

@ -18,10 +18,13 @@
*/
/**
* @file ARMCM3/STM32F103/cmparams.h
* @brief ARM Cortex-M3 STM32 specific parameters.
* @file ARMCMx/STM32F103/cmparams.h
* @brief ARM Cortex-M3 STM32F10x specific parameters.
*
* @addtogroup ARMCM3_STM32F103
* @defgroup ARMCMx_STM32F10x STM32F10x specific parameters
* @ingroup ARMCMx
* @details This file contains the Cortex-M3 specific parameters for the
* STM32F10x platform.
* @{
*/

14
os/ports/GCC/ARMCMx/STM32F103/port.mk
View File

@ -1,10 +1,10 @@
# List of the ChibiOS/RT Cortex-M3 port files.
PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCM3/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCM3/nvic.c \
${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis/core_cm3.c
PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c
PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCM3/crt0.s
PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCM3 \
${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103 \
${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F103 \
${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis

6
os/ports/GCC/ARMCMx/chcore.c
View File

@ -18,10 +18,10 @@
*/
/**
* @file ARMCM3/chcore.c
* @brief ARM Cortex-M3 architecture port code.
* @file ARMCMx/chcore.c
* @brief ARM Cortex-Mx architecture port code.
*
* @addtogroup ARMCM3_CORE
* @addtogroup ARMCMx_CORE
* @{
*/

6
os/ports/GCC/ARMCMx/chcore.h
View File

@ -18,10 +18,10 @@
*/
/**
* @file ARMCM3/chcore.h
* @brief ARM Cortex-M3 architecture port macros and structures.
* @file ARMCMx/chcore.h
* @brief ARM Cortex-Mx architecture port macros and structures.
*
* @addtogroup ARMCM3_CORE
* @addtogroup ARMCMx_CORE
* @{
*/

4
os/ports/GCC/ARMCMx/chtypes.h
View File

@ -18,9 +18,9 @@
*/
/**
* @file ARMCM3/chtypes.h
* @file ARMCMx/chtypes.h
* @brief ARM Cortex-M3 architecture port system types.
* @addtogroup ARMCM3_CORE
* @addtogroup ARMCMx_CORE
* @{
*/

6
os/ports/GCC/ARMCMx/crt0.s
View File

@ -18,9 +18,9 @@
*/
/**
* @file ARMCM3/crt0.s
* @brief Generic ARM Cortex-M3 startup file for ChibiOS/RT.
* @addtogroup ARMCM3_CORE
* @file ARMCMx/crt0.s
* @brief Generic ARM Cortex-Mx startup file for ChibiOS/RT.
* @addtogroup ARMCMx_CORE
* @{
*/
/** @cond never */

6
os/ports/GCC/ARMCMx/nvic.c
View File

@ -18,9 +18,9 @@
*/
/**
* @file ARMCM3/nvic.c
* @brief Cortex-M3 NVIC support code.
* @addtogroup ARMCM3_NVIC
* @file ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code.
* @addtogroup ARMCMx_NVIC
* @{
*/

6
os/ports/GCC/ARMCMx/nvic.h
View File

@ -18,9 +18,9 @@
*/
/**
* @file ARMCM3/nvic.h
* @brief Cortex-M3 NVIC support macros and structures.
* @addtogroup ARMCM3_NVIC
* @file ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures.
* @addtogroup ARMCMx_NVIC
* @{
*/

80
os/ports/GCC/ARMCMx/port.dox
View File

@ -18,35 +18,35 @@
*/
/**
* @defgroup ARMCM3 ARM Cortex-M3
* @details The ARM Cortex-M3 architecture is quite complex for a
* microcontroller and some explanations are required about the port choices.
* @defgroup ARMCMx ARM Cortex-Mx
* @details This port supports the ARM Cortex-Mx architectures, specifically
* the Cortex-M0 and the Cortex-M3.
*
* @section ARMCM3_STATES Mapping of the System States in the ARM Cortex-M3 port
* @section ARMCMx_STATES Mapping of the System States in the ARM Cortex-Mx port
* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
* Cortex-M3 port:
* Cortex-Mx port:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
* set at @p BASEPRI_USER level, interrupts are not masked. The processor
* is running in thread-privileged mode.
* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
* processor is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
* any interrupt source with lower or equal priority. The processor
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
* is running in thread-privileged mode.
* - <b>Sleep</b>. This state is entered with the execution of the specific
* instruction @p <b>wfi</b>.
* - <b>S-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
* any interrupt source with lower or equal priority. The processor
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>I-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
* any interrupt source with lower or equal priority. The processor
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in exception-privileged mode.
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
* not globally masked but only interrupts with higher priority can preempt
@ -54,15 +54,15 @@
* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
* but it is not possible to switch to the I-Locked state because fast
* interrupts can preempt the kernel critical zone.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered to be in this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
* .
* @section ARMCM3_NOTES The ARM Cortex-M3 port notes
* The ARM Cortex-M3 port is organized as follow:
* @section ARMCMx_NOTES The ARM Cortex-Mx port notes
* The ARM Cortex-Mx port is organized as follow:
* - The @p main() function is invoked in thread-privileged mode.
* - Each thread has a private process stack, the system has a single main
* stack where all the interrupts and exceptions are processed.
@ -70,8 +70,8 @@
* to be zero.
* - The threads are started in thread-privileged mode with BASEPRI level
* 0x00 (disabled).
* - The kernel raises its BASEPRI level to @p BASEPRI_KERNEL in order to
* protect the kernel data structures.
* - The kernel raises its BASEPRI level to @p CORTEX_BASEPRI_KERNEL in order
* to protect the kernel data structures.
* - Interrupt nesting and the other advanced NVIC features are supported.
* - The SVC instruction and vector, with parameter #0, is internally used
* for commanded context switching.<br>
@ -83,9 +83,9 @@
*/
/**
* @defgroup ARMCM3_CONF Configuration Options
* @brief ARM Cortex-M3 Configuration Options.
* @details The ARMCM3 port allows some architecture-specific configurations
* @defgroup ARMCMx_CONF Configuration Options
* @brief ARM Cortex-Mx Configuration Options.
* @details The ARMCMx port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
* command line:
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
@ -94,35 +94,35 @@
* In the current implementation this value is guaranteed to be zero so
* there is no need to modify this value unless changes are done at the
* interrupts handling code.
* - @p BASEPRI_USER, this is the @p BASEPRI value for the user threads. The
* default value is @p 0 (disabled).<br>
* - @p CORTEX_BASEPRI_USER, this is the @p BASEPRI value for the user threads.
* The default value is @p 0 (disabled).<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* - @p BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock code.
* The default value is 0x40.<br>
* Cortex-Mx technical reference manual for a detailed description.
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
* code.<br>
* Code running at higher priority levels must not invoke any OS API.<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* Cortex-Mx technical reference manual for a detailed description.
* - @p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p <b>wfi</b>
* instruction from within the idle loop. This is defaulted to 0 because
* it can create problems with some debuggers. Setting this option to 1
* reduces the system power requirements.
* .
* @ingroup ARMCM3
* @ingroup ARMCMx
*/
/**
* @defgroup ARMCM3_CORE Core Port Implementation
* @brief ARM Cortex-M3 specific port code, structures and macros.
* @defgroup ARMCMx_CORE Core Port Implementation
* @brief ARM Cortex-Mx specific port code, structures and macros.
*
* @ingroup ARMCM3
* @ingroup ARMCMx
*/
/**
* @defgroup ARMCM3_STARTUP Startup Support
* @brief ARM Cortex-M3 startup code support.
* @defgroup ARMCMx_STARTUP Startup Support
* @brief ARM Cortex-Mx startup code support.
* @details ChibiOS/RT provides its own generic startup file for the ARM
* Cortex-M3 port.
* Cortex-Mx port.
* Of course it is not mandatory to use it but care should be taken about the
* startup phase details.
*
@ -158,13 +158,13 @@
* - @p _bss_start BSS start location.
* - @p _bss_end BSS end location +1.
* .
* @ingroup ARMCM3
* @file ARMCM3/crt0.s Startup code.
* @ingroup ARMCMx
* @file ARMCMx/crt0.s Startup code.
*/
/**
* @defgroup ARMCM3_NVIC NVIC Support
* @brief ARM Cortex-M3 NVIC support.
* @defgroup ARMCMx_NVIC NVIC Support
* @brief ARM Cortex-Mx NVIC support.
*
* @ingroup ARMCM3
* @ingroup ARMCMx
*/

1
readme.txt
View File

@ -84,6 +84,7 @@
- OPT: Simplified the implementation of chSchYieldS() and made it a macro.
The previous implementation was probably overkill and took too much space
even if a bit faster.
- CHANGE: Modified the Cortex-M3 port to be a more generic Cortex-Mx port.
- CHANGE: Exiting from a chCondWaitTimeout() because a timeout now does not
re-acquire the mutex, ownership is lost.
- CHANGE: The module documentation has been moved from the kernel.dox file

6
testhal/STM32/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
@ -102,7 +102,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
DDEFS = -DSTM32F10X_MD
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =

44
testhal/STM32/mcuconf.h
View File

@ -25,28 +25,34 @@
* is enabled in halconf.h.
*
* IRQ priorities:
* 0xF0 Lowest, priority level reserved for PENDSV.
* 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK).
* 0x30 Used by SVCALL, do not share.
* 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it.
* 15 Lowest, priority level reserved for PENDSV.
* 14...4 Normal IRQs priority levels (0x80 used by SYSTICK).
* 3 Used by SVCALL, do not share.
* 2...0 Fast interrupts, can preempt the kernel but cannot use it
* directly.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
/*
* HAL driver system settings.
*/
#define STM32_SYSCLK 72
/*
* ADC driver system settings.
*/
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
#define STM32_ADC1_IRQ_PRIORITY 0x50
#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
#define STM32_CAN1_IRQ_PRIORITY 0xB0
#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
/*
* PWM driver system settings.
@ -55,10 +61,10 @@
#define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
#define STM32_PWM1_IRQ_PRIORITY 0x70
#define STM32_PWM2_IRQ_PRIORITY 0x70
#define STM32_PWM3_IRQ_PRIORITY 0x70
#define STM32_PWM4_IRQ_PRIORITY 0x70
#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
/*
* SERIAL driver system settings.
@ -66,9 +72,17 @@
#define USE_STM32_USART1 FALSE
#define USE_STM32_USART2 TRUE
#define USE_STM32_USART3 FALSE
#define STM32_USART1_PRIORITY 0xC0
#define STM32_USART2_PRIORITY 0xC0
#define STM32_USART3_PRIORITY 0xC0
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
#endif
/*
* SPI driver system settings.
@ -77,6 +91,6 @@
#define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
#define STM32_SPI1_IRQ_PRIORITY 0xA0
#define STM32_SPI2_IRQ_PRIORITY 0xA0
#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()