diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/.cproject b/demos/nil/NIL-STM32F373-STM32373C_EVAL/.cproject new file mode 100644 index 000000000..a32ef55e6 --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/.cproject @@ -0,0 +1,213 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/.project b/demos/nil/NIL-STM32F373-STM32373C_EVAL/.project new file mode 100644 index 000000000..8cd970a0f --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/.project @@ -0,0 +1,90 @@ + + + NIL-STM32F373-STM32373C_EVAL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/Makefile b/demos/nil/NIL-STM32F373-STM32373C_EVAL/Makefile new file mode 100644 index 000000000..9400ff789 --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/Makefile @@ -0,0 +1,225 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/ports/STM32F37x/platform.mk +include $(CHIBIOS)/os/nil/nil.mk +include $(CHIBIOS)/os/nil/osal/osal.mk +include $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(OSALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE + DADEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE + DADEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/rules.mk diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/halconf.h b/demos/nil/NIL-STM32F373-STM32373C_EVAL/halconf.h new file mode 100644 index 000000000..d63d30523 --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/halconf.h @@ -0,0 +1,305 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/main.c b/demos/nil/NIL-STM32F373-STM32373C_EVAL/main.c new file mode 100644 index 000000000..71e500143 --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/main.c @@ -0,0 +1,108 @@ +/* + Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio. + + This file is part of Nil RTOS. + + Nil RTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Nil RTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "hal.h" +#include "nil.h" + +/* + * Thread 1. + */ +THD_WORKING_AREA(waThread1, 128); +THD_FUNCTION(Thread1, arg) { + + (void)arg; + + while (true) { + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(250); + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(250); + } +} + +/* + * Thread 2. + */ +THD_WORKING_AREA(waThread2, 128); +THD_FUNCTION(Thread2, arg) { + + (void)arg; + + while (true) { + palSetPad(GPIOC, GPIOC_LED2); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED2); + chThdSleepMilliseconds(500); + } +} + +/* + * Thread 3. + */ +THD_WORKING_AREA(waThread3, 128); +THD_FUNCTION(Thread3, arg) { + + (void)arg; + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA9 and PA10 are routed to USART1. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); /* USART1 RX. */ + + while (true) { + chnWrite(&SD2, (const uint8_t *)"Hello World!\r\n", 14); + chThdSleepMilliseconds(2000); + } +} + +/* + * Threads static table, one entry per thread. The number of entries must + * match NIL_CFG_NUM_THREADS. + */ +THD_TABLE_BEGIN + THD_TABLE_ENTRY(waThread1, "blinker1", Thread1, NULL) + THD_TABLE_ENTRY(waThread2, "blinker2", Thread2, NULL) + THD_TABLE_ENTRY(waThread3, "hello", Thread3, NULL) +THD_TABLE_END + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* This is now the idle thread loop, you may perform here a low priority + task but you must never try to sleep or wait in this loop. Note that + this tasks runs at the lowest priority level so any instruction added + here will be executed after all other tasks have been started.*/ + while (true) { + } +} diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/mcuconf.h b/demos/nil/NIL-STM32F373-STM32373C_EVAL/mcuconf.h new file mode 100644 index 000000000..6929b9c32 --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/nil/NIL-STM32F373-STM32373C_EVAL/nilconf.h b/demos/nil/NIL-STM32F373-STM32373C_EVAL/nilconf.h new file mode 100644 index 000000000..5276a3f2a --- /dev/null +++ b/demos/nil/NIL-STM32F373-STM32373C_EVAL/nilconf.h @@ -0,0 +1,112 @@ +/* + Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio. + + This file is part of Nil RTOS. + + Nil RTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Nil RTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file nilconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _NILCONF_H_ +#define _NILCONF_H_ + +/** + * @brief Number of user threads in the application. + * @note This number is not inclusive of the idle thread which is + * Implicitly handled. + */ +#define NIL_CFG_NUM_THREADS 3 + +/** + * @brief System tick frequency. + */ +#define NIL_CFG_ST_FREQUENCY 50000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define NIL_CFG_TIMEDELTA 2 + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define NIL_CFG_USE_EVENTS TRUE + +/** + * @brief System assertions. + */ +#define NIL_CFG_ENABLE_ASSERTS FALSE + +/** + * @brief Stack check. + */ +#define NIL_CFG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define NIL_CFG_THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + */ +#define NIL_CFG_THREAD_EXT_INIT_HOOK(tr) { \ + /* Add custom threads initialization code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define NIL_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define NIL_CFG_IDLE_LEAVE_HOOK() { \ +} + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in nilcore.h). */ +/*===========================================================================*/ + +#endif /* _NILCONF_H_ */ + +/** @} */ diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.c b/os/hal/boards/ST_STM32373C_EVAL/board.c index baafd6550..ef05d62a7 100644 --- a/os/hal/boards/ST_STM32373C_EVAL/board.c +++ b/os/hal/boards/ST_STM32373C_EVAL/board.c @@ -14,7 +14,6 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" #if HAL_USE_PAL || defined(__DOXYGEN__) diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.mk b/os/hal/boards/ST_STM32373C_EVAL/board.mk index 98a37d006..271a37fd1 100644 --- a/os/hal/boards/ST_STM32373C_EVAL/board.mk +++ b/os/hal/boards/ST_STM32373C_EVAL/board.mk @@ -1,5 +1,5 @@ # List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/ST_STM32373C_EVAL/board.c +BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32373C_EVAL/board.c # Required include directories -BOARDINC = ${CHIBIOS}/boards/ST_STM32373C_EVAL +BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32373C_EVAL diff --git a/os/hal/ports/STM32F30x/stm32_registry.h b/os/hal/ports/STM32F30x/stm32_registry.h index 7487620ef..75c72d396 100644 --- a/os/hal/ports/STM32F30x/stm32_registry.h +++ b/os/hal/ports/STM32F30x/stm32_registry.h @@ -35,11 +35,8 @@ */ /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE - #define STM32_HAS_ADC2 TRUE - #define STM32_HAS_ADC3 TRUE - #define STM32_HAS_ADC4 TRUE #define STM32_HAS_SDADC1 FALSE diff --git a/os/hal/ports/STM32F37x/adc_lld.c b/os/hal/ports/STM32F37x/adc_lld.c index ebb6da7ec..72514ded6 100644 --- a/os/hal/ports/STM32F37x/adc_lld.c +++ b/os/hal/ports/STM32F37x/adc_lld.c @@ -15,14 +15,13 @@ */ /** - * @file STM32F4xx/adc_lld.c - * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source. + * @file STM32F37x/adc_lld.c + * @brief STM32F37x ADC subsystem low level driver source. * * @addtogroup ADC * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_ADC || defined(__DOXYGEN__) @@ -132,7 +131,7 @@ static void adc_lld_reconfig(ADCDriver *adcp) { #endif /* STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC else { - chDbgAssert(FALSE, "adc_lld_start(), #5", "invalid state"); + osalDbgAssert(FALSE, "invalid state"); } #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ } @@ -227,16 +226,16 @@ static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { * * @isr */ -CH_IRQ_HANDLER(Vector88) { +OSAL_IRQ_HANDLER(Vector88) { uint32_t sr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); sr = ADC1->SR; ADC1->SR = 0; adc_lld_serve_interrupt(&ADCD1, sr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ADC_USE_ADC1 */ @@ -246,16 +245,16 @@ CH_IRQ_HANDLER(Vector88) { * * @isr */ -CH_IRQ_HANDLER(Vector134) { +OSAL_IRQ_HANDLER(Vector134) { uint32_t isr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); isr = SDADC1->ISR; SDADC1->CLRISR = isr; sdadc_lld_serve_interrupt(&SDADCD1, isr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ADC_USE_SDADC1 */ @@ -265,16 +264,16 @@ CH_IRQ_HANDLER(Vector134) { * * @isr */ -CH_IRQ_HANDLER(Vector138) { +OSAL_IRQ_HANDLER(Vector138) { uint32_t isr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); isr = SDADC2->ISR; SDADC2->CLRISR = isr; sdadc_lld_serve_interrupt(&SDADCD2, isr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ADC_USE_SDADC2 */ @@ -284,16 +283,16 @@ CH_IRQ_HANDLER(Vector138) { * * @isr */ -CH_IRQ_HANDLER(Vector13C) { +OSAL_IRQ_HANDLER(Vector13C) { uint32_t isr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); isr = SDADC3->ISR; SDADC3->CLRISR = isr; sdadc_lld_serve_interrupt(&SDADCD3, isr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ADC_USE_SDADC3 */ @@ -322,7 +321,7 @@ void adc_lld_init(void) { STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); + nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY); #endif #if STM32_ADC_USE_SDADC1 @@ -339,8 +338,7 @@ void adc_lld_init(void) { STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC1_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY)); + nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY); #endif #if STM32_ADC_USE_SDADC2 @@ -357,8 +355,7 @@ void adc_lld_init(void) { STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC2_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY)); + nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY); #endif #if STM32_ADC_USE_SDADC3 @@ -375,8 +372,7 @@ void adc_lld_init(void) { STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC3_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY)); + nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY); #endif } @@ -396,12 +392,11 @@ void adc_lld_start(ADCDriver *adcp) { if (adcp->state == ADC_STOP) { #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); rccEnableADC1(FALSE); } @@ -409,11 +404,11 @@ void adc_lld_start(ADCDriver *adcp) { #if STM32_ADC_USE_SDADC1 if (&SDADCD1 == adcp) { - bool_t b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC1EN; @@ -426,11 +421,11 @@ void adc_lld_start(ADCDriver *adcp) { #if STM32_ADC_USE_SDADC2 if (&SDADCD2 == adcp) { - bool_t b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC2EN; @@ -443,11 +438,11 @@ void adc_lld_start(ADCDriver *adcp) { #if STM32_ADC_USE_SDADC3 if (&SDADCD3 == adcp) { - bool_t b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated"); + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); rccEnableSDADC1(FALSE); PWR->CR |= PWR_CR_SDADC3EN; @@ -598,7 +593,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { #endif /* STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC else { - chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state"); + osalDbgAssert(FALSE, "invalid state"); } #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ } @@ -632,10 +627,10 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { */ void adcSTM32Calibrate(ADCDriver *adcp) { - chDbgAssert((adcp->state == ADC_READY) || + osalDbgAssert((adcp->state == ADC_READY) || (adcp->state == ADC_COMPLETE) || (adcp->state == ADC_ERROR), - "adcSTM32Calibrate(), #1", "not ready"); + "not ready"); #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC if (adcp->adc != NULL) @@ -673,7 +668,7 @@ void adcSTM32Calibrate(ADCDriver *adcp) { #endif /* STM32_ADC_USE_SDADC */ #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC else { - chDbgAssert(FALSE, "adcSTM32Calibrate(), #2", "invalid state"); + osalDbgAssert(FALSE, "invalid state"); } #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ } diff --git a/os/hal/ports/STM32F37x/ext_lld_isr.c b/os/hal/ports/STM32F37x/ext_lld_isr.c index f43f3aecb..642f6f8c4 100644 --- a/os/hal/ports/STM32F37x/ext_lld_isr.c +++ b/os/hal/ports/STM32F37x/ext_lld_isr.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_EXT || defined(__DOXYGEN__) @@ -55,14 +54,14 @@ * * @isr */ -CH_IRQ_HANDLER(Vector58) { +OSAL_IRQ_HANDLER(Vector58) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 0); EXTD1.config->channels[0].cb(&EXTD1, 0); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -72,14 +71,14 @@ CH_IRQ_HANDLER(Vector58) { * * @isr */ -CH_IRQ_HANDLER(Vector5C) { +OSAL_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 1); EXTD1.config->channels[1].cb(&EXTD1, 1); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -89,14 +88,14 @@ CH_IRQ_HANDLER(Vector5C) { * * @isr */ -CH_IRQ_HANDLER(Vector60) { +OSAL_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 2); EXTD1.config->channels[2].cb(&EXTD1, 2); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -106,14 +105,14 @@ CH_IRQ_HANDLER(Vector60) { * * @isr */ -CH_IRQ_HANDLER(Vector64) { +OSAL_IRQ_HANDLER(Vector64) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 3); EXTD1.config->channels[3].cb(&EXTD1, 3); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -123,14 +122,14 @@ CH_IRQ_HANDLER(Vector64) { * * @isr */ -CH_IRQ_HANDLER(Vector68) { +OSAL_IRQ_HANDLER(Vector68) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 4); EXTD1.config->channels[4].cb(&EXTD1, 4); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -140,10 +139,10 @@ CH_IRQ_HANDLER(Vector68) { * * @isr */ -CH_IRQ_HANDLER(Vector9C) { +OSAL_IRQ_HANDLER(Vector9C) { uint32_t pr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); EXTI->PR = pr; @@ -158,7 +157,7 @@ CH_IRQ_HANDLER(Vector9C) { if (pr & (1 << 9)) EXTD1.config->channels[9].cb(&EXTD1, 9); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -168,10 +167,10 @@ CH_IRQ_HANDLER(Vector9C) { * * @isr */ -CH_IRQ_HANDLER(VectorE0) { +OSAL_IRQ_HANDLER(VectorE0) { uint32_t pr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15)); @@ -189,7 +188,7 @@ CH_IRQ_HANDLER(VectorE0) { if (pr & (1 << 15)) EXTD1.config->channels[15].cb(&EXTD1, 15); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -199,14 +198,14 @@ CH_IRQ_HANDLER(VectorE0) { * * @isr */ -CH_IRQ_HANDLER(Vector44) { +OSAL_IRQ_HANDLER(Vector44) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 16); EXTD1.config->channels[16].cb(&EXTD1, 16); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -216,14 +215,14 @@ CH_IRQ_HANDLER(Vector44) { * * @isr */ -CH_IRQ_HANDLER(VectorE4) { +OSAL_IRQ_HANDLER(VectorE4) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 17); EXTD1.config->channels[17].cb(&EXTD1, 17); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -233,14 +232,14 @@ CH_IRQ_HANDLER(VectorE4) { * * @isr */ -CH_IRQ_HANDLER(VectorE8) { +OSAL_IRQ_HANDLER(VectorE8) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 18); EXTD1.config->channels[18].cb(&EXTD1, 18); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -250,14 +249,14 @@ CH_IRQ_HANDLER(VectorE8) { * * @isr */ -CH_IRQ_HANDLER(Vector48) { +OSAL_IRQ_HANDLER(Vector48) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 19); EXTD1.config->channels[19].cb(&EXTD1, 19); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -267,14 +266,14 @@ CH_IRQ_HANDLER(Vector48) { * * @isr */ -CH_IRQ_HANDLER(Vector4C) { +OSAL_IRQ_HANDLER(Vector4C) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 20); EXTD1.config->channels[20].cb(&EXTD1, 20); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -284,10 +283,10 @@ CH_IRQ_HANDLER(Vector4C) { * * @isr */ -CH_IRQ_HANDLER(Vector140) { +OSAL_IRQ_HANDLER(Vector140) { uint32_t pr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); pr = EXTI->PR & ((1 << 21) | (1 << 22)); EXTI->PR = pr; @@ -296,7 +295,7 @@ CH_IRQ_HANDLER(Vector140) { if (pr & (1 << 22)) EXTD1.config->channels[22].cb(&EXTD1, 22); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -311,32 +310,19 @@ CH_IRQ_HANDLER(Vector140) { */ void ext_lld_exti_irq_enable(void) { - nvicEnableVector(EXTI0_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); - nvicEnableVector(EXTI1_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); - nvicEnableVector(EXTI2_TS_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); - nvicEnableVector(EXTI3_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); - nvicEnableVector(EXTI4_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); - nvicEnableVector(EXTI9_5_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); - nvicEnableVector(EXTI15_10_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); - nvicEnableVector(PVD_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); - nvicEnableVector(RTC_Alarm_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); - nvicEnableVector(USBWakeUp_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); - nvicEnableVector(TAMPER_STAMP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); - nvicEnableVector(RTC_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); - nvicEnableVector(COMP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY)); + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_TS_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); + nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); } /** diff --git a/os/hal/ports/STM32F37x/hal_lld.c b/os/hal/ports/STM32F37x/hal_lld.c index a47ab59fc..6234137b0 100644 --- a/os/hal/ports/STM32F37x/hal_lld.c +++ b/os/hal/ports/STM32F37x/hal_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /*===========================================================================*/ @@ -103,17 +102,6 @@ void hal_lld_init(void) { rccResetAPB1(0xFFFFFFFF); rccResetAPB2(0xFFFFFFFF); - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - /* PWR clock enabled.*/ rccEnablePWRInterface(FALSE); diff --git a/os/hal/ports/STM32F37x/hal_lld.h b/os/hal/ports/STM32F37x/hal_lld.h index 96659baf3..2d7a0dac1 100644 --- a/os/hal/ports/STM32F37x/hal_lld.h +++ b/os/hal/ports/STM32F37x/hal_lld.h @@ -1007,6 +1007,7 @@ typedef uint32_t halrtcnt_t; /*===========================================================================*/ /* STM32 ISR, DMA and RCC helpers.*/ +#include "nvic.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32F37x/platform.mk b/os/hal/ports/STM32F37x/platform.mk index 1cd7f9260..fbcaaa80f 100644 --- a/os/hal/ports/STM32F37x/platform.mk +++ b/os/hal/ports/STM32F37x/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32F37x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \ +PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \ ${CHIBIOS}/os/hal/ports/STM32F37x/hal_lld.c \ ${CHIBIOS}/os/hal/ports/STM32F37x/adc_lld.c \ ${CHIBIOS}/os/hal/ports/STM32F37x/ext_lld_isr.c \ @@ -12,12 +13,14 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/gpt_lld.c \ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/icu_lld.c \ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/pwm_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/st_lld.c \ ${CHIBIOS}/os/hal/ports/STM32/USARTv2/serial_lld.c \ ${CHIBIOS}/os/hal/ports/STM32/USARTv2/uart_lld.c \ ${CHIBIOS}/os/hal/ports/STM32/USBv1/usb_lld.c # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/STM32F37x \ +PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS}/os/hal/ports/STM32F37x \ ${CHIBIOS}/os/hal/ports/STM32 \ ${CHIBIOS}/os/hal/ports/STM32/GPIOv2 \ ${CHIBIOS}/os/hal/ports/STM32/I2Cv2 \ diff --git a/os/hal/ports/STM32F37x/stm32_dma.c b/os/hal/ports/STM32F37x/stm32_dma.c index b9ce0ddfc..362348957 100644 --- a/os/hal/ports/STM32F37x/stm32_dma.c +++ b/os/hal/ports/STM32F37x/stm32_dma.c @@ -29,7 +29,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /* The following macro is only defined if some driver requiring DMA services @@ -116,17 +115,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; * * @isr */ -CH_IRQ_HANDLER(Vector6C) { +OSAL_IRQ_HANDLER(Vector6C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[0].dma_func) dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -134,17 +133,17 @@ CH_IRQ_HANDLER(Vector6C) { * * @isr */ -CH_IRQ_HANDLER(Vector70) { +OSAL_IRQ_HANDLER(Vector70) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[1].dma_func) dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -152,17 +151,17 @@ CH_IRQ_HANDLER(Vector70) { * * @isr */ -CH_IRQ_HANDLER(Vector74) { +OSAL_IRQ_HANDLER(Vector74) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[2].dma_func) dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -170,17 +169,17 @@ CH_IRQ_HANDLER(Vector74) { * * @isr */ -CH_IRQ_HANDLER(Vector78) { +OSAL_IRQ_HANDLER(Vector78) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[3].dma_func) dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -188,17 +187,17 @@ CH_IRQ_HANDLER(Vector78) { * * @isr */ -CH_IRQ_HANDLER(Vector7C) { +OSAL_IRQ_HANDLER(Vector7C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[4].dma_func) dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -206,17 +205,17 @@ CH_IRQ_HANDLER(Vector7C) { * * @isr */ -CH_IRQ_HANDLER(Vector80) { +OSAL_IRQ_HANDLER(Vector80) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 20; if (dma_isr_redir[5].dma_func) dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -224,17 +223,17 @@ CH_IRQ_HANDLER(Vector80) { * * @isr */ -CH_IRQ_HANDLER(Vector84) { +OSAL_IRQ_HANDLER(Vector84) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 24; if (dma_isr_redir[6].dma_func) dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -242,17 +241,17 @@ CH_IRQ_HANDLER(Vector84) { * * @isr */ -CH_IRQ_HANDLER(Vector120) { +OSAL_IRQ_HANDLER(Vector120) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[7].dma_func) dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -260,17 +259,17 @@ CH_IRQ_HANDLER(Vector120) { * * @isr */ -CH_IRQ_HANDLER(Vector124) { +OSAL_IRQ_HANDLER(Vector124) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[8].dma_func) dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -278,17 +277,17 @@ CH_IRQ_HANDLER(Vector124) { * * @isr */ -CH_IRQ_HANDLER(Vector128) { +OSAL_IRQ_HANDLER(Vector128) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[9].dma_func) dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -296,17 +295,17 @@ CH_IRQ_HANDLER(Vector128) { * * @isr */ -CH_IRQ_HANDLER(Vector12C) { +OSAL_IRQ_HANDLER(Vector12C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[10].dma_func) dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -314,17 +313,17 @@ CH_IRQ_HANDLER(Vector12C) { * * @isr */ -CH_IRQ_HANDLER(Vector130) { +OSAL_IRQ_HANDLER(Vector130) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[11].dma_func) dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /*===========================================================================*/ @@ -374,12 +373,12 @@ void dmaInit(void) { * * @special */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { +bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + osalDbgCheck(dmastp != NULL); /* Checks if the stream is already taken.*/ if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) @@ -424,11 +423,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, */ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + osalDbgCheck(dmastp != NULL); /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); + osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "not allocated"); /* Disables the associated IRQ vector.*/ nvicDisableVector(dmastp->vector); diff --git a/os/hal/ports/STM32F37x/stm32_dma.h b/os/hal/ports/STM32F37x/stm32_dma.h index 79d295598..e77b3ba77 100644 --- a/os/hal/ports/STM32F37x/stm32_dma.h +++ b/os/hal/ports/STM32F37x/stm32_dma.h @@ -392,10 +392,10 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; extern "C" { #endif void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); + bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); void dmaStreamRelease(const stm32_dma_stream_t *dmastp); #ifdef __cplusplus } diff --git a/os/hal/ports/STM32F37x/stm32_registry.h b/os/hal/ports/STM32F37x/stm32_registry.h index 8f0842263..3a7cdfaf2 100644 --- a/os/hal/ports/STM32F37x/stm32_registry.h +++ b/os/hal/ports/STM32F37x/stm32_registry.h @@ -34,172 +34,164 @@ * @{ */ /* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) -#define STM32_ADC1_DMA_CHN 0x00000000 +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE -#define STM32_HAS_ADC2 FALSE -#define STM32_ADC2_DMA_MSK 0 -#define STM32_ADC2_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC3 FALSE -#define STM32_ADC3_DMA_MSK 0 -#define STM32_ADC3_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC4 FALSE -#define STM32_ADC4_DMA_MSK 0 -#define STM32_ADC4_DMA_CHN 0x00000000 - -#define STM32_HAS_SDADC1 TRUE -#define STM32_SDADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SDADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_SDADC2 TRUE -#define STM32_SDADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SDADC2_DMA_CHN 0x00000000 - -#define STM32_HAS_SDADC3 TRUE -#define STM32_SDADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SDADC3_DMA_CHN 0x00000000 +#define STM32_HAS_SDADC1 TRUE +#define STM32_HAS_SDADC2 TRUE +#define STM32_HAS_SDADC3 TRUE /* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ -#define STM32_HAS_DAC TRUE +#define STM32_HAS_DAC1 TRUE +#define STM32_HAS_DAC2 TRUE /* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE /* ETH attributes.*/ -#define STM32_HAS_ETH FALSE +#define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 29 +#define STM32_EXTI_NUM_CHANNELS 29 /* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE /* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 +#define STM32_HAS_I2C3 FALSE /* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_IS_CALENDAR TRUE +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR TRUE /* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE +#define STM32_HAS_SDIO FALSE /* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) /* TIM attributes.*/ -#define STM32_HAS_TIM1 FALSE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 TRUE -#define STM32_HAS_TIM13 TRUE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 TRUE -#define STM32_HAS_TIM19 TRUE +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 2 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 2 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 2 + +#define STM32_HAS_TIM18 TRUE +#define STM32_TIM18_IS_32BITS FALSE +#define STM32_TIM18_CHANNELS 0 + +#define STM32_HAS_TIM19 TRUE +#define STM32_TIM19_IS_32BITS FALSE +#define STM32_TIM19_CHANNELS 4 + +#define STM32_HAS_TIM1 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE /* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 +#define STM32_HAS_USART3 TRUE +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE /* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE /** @} */ #endif /* _STM32_REGISTRY_H_ */