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Cortex-M0 improvements for RVCT. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2802 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2011-03-06 10:32:00 +00:00
parent 30c73db82f
commit 3964ec0195
4 changed files with 40 additions and 59 deletions
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26
docs/reports/LPC1114-48-RVCT.txt
View File

@ -90,7 +90,7 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic APIs, registry and references)
--- Result: SUCCESS
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--- Test Case 10.1 (Queues, input queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
@ -98,51 +98,51 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
--- Score : 119522 msgs/S, 239044 ctxswc/S
--- Score : 121347 msgs/S, 242694 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
--- Score : 102156 msgs/S, 204312 ctxswc/S
--- Score : 102162 msgs/S, 204324 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
--- Score : 102595 msgs/S, 205190 ctxswc/S
--- Score : 102162 msgs/S, 204324 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
--- Score : 375344 ctxswc/S
--- Score : 377584 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 79025 threads/S
--- Score : 78768 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 111705 threads/S
--- Score : 112764 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 33692 reschedules/S, 202152 ctxswc/S
--- Score : 33088 reschedules/S, 198528 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
--- Score : 249324 ctxswc/S
--- Score : 249336 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
--- Score : 264832 bytes/S
--- Score : 270084 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
--- Score : 303508 timers/S
--- Score : 303522 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
--- Score : 614828 wait+signal/S
--- Score : 603212 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
--- Score : 381660 lock+unlock/S
--- Score : 372744 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)

5
os/ports/RVCT/ARMCMx/chcore_v6m.c
View File

@ -27,11 +27,6 @@
#include "ch.h"
/**
* @brief PC register temporary storage.
*/
regarm_t _port_saved_pc;
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.

22
os/ports/RVCT/ARMCMx/chcore_v6m.h
View File

@ -32,10 +32,8 @@
/* Port implementation part. */
/*===========================================================================*/
/**
* @brief Cortex-Mx exception context.
*/
struct cmxctx {
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
@ -46,18 +44,6 @@ struct cmxctx {
regarm_t xpsr;
};
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t xpsr;
regarm_t r12;
regarm_t lr;
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t pc;
};
struct intctx {
regarm_t r8;
regarm_t r9;
@ -223,10 +209,6 @@ struct intctx {
*/
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#if !defined(__DOXYGEN__)
extern regarm_t _port_saved_pc;
#endif
#ifdef __cplusplus
extern "C" {
#endif

46
os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
View File

@ -27,6 +27,7 @@
EXTCTX_SIZE EQU 32
CONTEXT_OFFSET EQU 12
SCB_ICSR EQU 0xE000ED04
PRESERVE8
THUMB
@ -35,8 +36,6 @@ CONTEXT_OFFSET EQU 12
IMPORT chThdExit
IMPORT chSchIsRescRequiredExI
IMPORT chSchDoRescheduleI
IMPORT _port_saved_pc
IMPORT _port_irq_nesting
/*
* Performs a context switch between two threads.
@ -73,29 +72,32 @@ _port_thread_start PROC
bl chThdExit
ENDP
/*
* NMI vector.
* The NMI vector is used for exception mode re-entering after a context
* switch.
*/
EXPORT NMIVector
NMIVector PROC
mrs r3, PSP
adds r3, r3, #32
msr PSP, r3
cpsie i
bx lr
ENDP
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
EXPORT _port_switch_from_isr
_port_switch_from_isr PROC
/* Note, saves r4 to make space for the PC.*/
push {r0, r1, r2, r3, r4}
mrs r0, APSR
mov r1, r12
push {r0, r1, lr}
ldr r0, =_port_saved_pc
ldr r0, [r0]
adds r0, r0, #1
str r0, [sp, #28]
bl chSchDoRescheduleI
pop {r0, r1, r2}
mov r12, r1
msr APSR, r0
mov lr, r2
pop {r0, r1, r2, r3}
cpsie i
pop {pc}
movs r3, #128
lsls r3, r3, #24
ldr r2, =SCB_ICSR
str r3, [r2, #0]
_waitnmi b _waitnmi
ENDP
/*
@ -115,11 +117,13 @@ stillnested
pop {r3, pc}
doresch
mrs r3, PSP
ldr r2, =_port_saved_pc
ldr r1, [r3, #24]
str r1, [r2]
subs r3, r3, #32
msr PSP, r3
ldr r2, =_port_switch_from_isr
str r2, [r3, #24]
movs r2, #128
lsls r2, r2, #17
str r2, [r3, #28]
pop {r3, pc}
ENDP