diff --git a/os/hal/platforms/STM32F30x/hal_lld.h b/os/hal/platforms/STM32F30x/hal_lld.h
index 625700ab5..b2d138877 100644
--- a/os/hal/platforms/STM32F30x/hal_lld.h
+++ b/os/hal/platforms/STM32F30x/hal_lld.h
@@ -253,10 +253,10 @@
 #define STM32_I2C2SW_SYSCLK     (1 << 5)    /**< I2C2 clock is SYSCLK.     */
 #define STM32_TIM1SW_MASK       (1 << 8)    /**< TIM1 clock source mask.   */
 #define STM32_TIM1SW_PCLK2      (0 << 8)    /**< TIM1 clock is PCLK2.      */
-#define STM32_TIM1SW_PLLX2      (1 << 10)   /**< TIM1 clock is PLL*2.      */
-#define STM32_TIM8SW_MASK       (1 << 10)   /**< TIM8 clock source mask.   */
-#define STM32_TIM8SW_PCLK2      (0 << 10)   /**< TIM8 clock is PCLK2.      */
-#define STM32_TIM8SW_PLLX2      (1 << 10)   /**< TIM8 clock is PLL*2.      */
+#define STM32_TIM1SW_PLLX2      (1 << 8)    /**< TIM1 clock is PLL*2.      */
+#define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
+#define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
+#define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
 #define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
 #define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
 #define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
diff --git a/readme.txt b/readme.txt
index f888d25f6..cea77c750 100644
--- a/readme.txt
+++ b/readme.txt
@@ -89,6 +89,9 @@
 *****************************************************************************
 
 *** 2.7.0 ***
+- FIX: Fixed wrong TIM1 and TIM8 macros in STM32F30x HAL driver (bug #473)
+  (backported to 2.6.4).
+- FIX: Fixed STM32 SDC driver clock activation issue (bug #464)(backported to
 - FIX: Fixed simulated IO message is corrupted in simulator (bug #468)
   (backported to 2.6.4).
 - FIX: Fixed TM32 SDC driver clock activation issue (bug #464)(backported to