From 3a208a4c8c48d4f038f32c8efb0994255a4b13f6 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 17 Oct 2016 09:31:26 +0000 Subject: [PATCH] Fixed bug #785. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9861 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F37x/hal_adc_lld.h | 2 +- readme.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h index d78389e30..ddea23640 100644 --- a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h +++ b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h @@ -35,7 +35,7 @@ * @name Triggers selection * @{ */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ /** @} */ /** diff --git a/readme.txt b/readme.txt index 6ee83650a..c87ec5a18 100644 --- a/readme.txt +++ b/readme.txt @@ -147,6 +147,8 @@ - RT: Merged RT4. - NIL: Merged NIL2. - NIL: Added STM32F7 demo. +- HAL: Fixed wrong bit offset in STM32F37x ADC_CR2_EXTSEL_SRC() macro + (bug #785)(backported to 16.1.6, 3.0.6). - RT: Fixed tick-less mode can fail in RT for very large delays (bug #784) (backported to 16.1.6, 3.0.6). - HAL: Fixed STM32L0xx CCIPR initialization (bug #783)