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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3320 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-09-16 17:38:22 +00:00
parent 46538d795b
commit 3a94137eb3
20 changed files with 121 additions and 148 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
os/hal/platforms/STM32/DMAv1/stm32_dma.c
View File

@ -437,10 +437,10 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enabling DMA clocks required by the current streams set.*/ /* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
RCC->AHBENR |= RCC_AHBENR_DMA1EN; rccEnableDMA1(FALSE);
#if STM32_HAS_DMA2 #if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
RCC->AHBENR |= RCC_AHBENR_DMA2EN; rccEnableDMA2(FALSE);
#endif #endif
/* Putting the stream in a safe state.*/ /* Putting the stream in a safe state.*/
@ -484,10 +484,10 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
/* Shutting down clocks that are no more required, if any.*/ /* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
RCC->AHBENR &= ~RCC_AHBENR_DMA1EN; rccDisableDMA1(FALSE);
#if STM32_HAS_DMA2 #if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
RCC->AHBENR &= ~RCC_AHBENR_DMA2EN; rccDisableDMA2(FALSE);
#endif #endif
} }

2
os/hal/platforms/STM32/GPIOv1/pal_lld.c
View File

@ -79,7 +79,7 @@ void _pal_lld_init(const PALConfig *config) {
/* /*
* Enables the GPIO related clocks. * Enables the GPIO related clocks.
*/ */
RCC->APB2ENR |= APB2_EN_MASK; rccEnableAPB2(APB2_EN_MASK, FALSE);
/* /*
* Initial GPIO setup. * Initial GPIO setup.

16
os/hal/platforms/STM32/GPIOv2/pal_lld.c
View File

@ -32,15 +32,14 @@
#if HAL_USE_PAL || defined(__DOXYGEN__) #if HAL_USE_PAL || defined(__DOXYGEN__)
#if defined(STM32L1XX_MD) #if defined(STM32L1XX_MD)
#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ #define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
#define AHB_LPEN_MASK AHB_EN_MASK
#elif defined(STM32F2XX) #elif defined(STM32F2XX)
#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ #define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
RCC_AHB1ENR_GPIOIEN) RCC_AHB1ENR_GPIOIEN)
#define AHB1_LPEN_MASK AHB1_EN_MASK #define AHB1_LPEN_MASK AHB1_EN_MASK
#else #else
@ -92,8 +91,7 @@ void _pal_lld_init(const PALConfig *config) {
* Enables the GPIO related clocks. * Enables the GPIO related clocks.
*/ */
#if defined(STM32L1XX_MD) #if defined(STM32L1XX_MD)
RCC->AHBENR |= AHB_EN_MASK; rccEnableAHB(AHB_EN_MASK, TRUE);
RCC->AHBLPENR |= AHB_LPEN_MASK;
#elif defined(STM32F2XX) #elif defined(STM32F2XX)
RCC->AHB1ENR |= AHB1_EN_MASK; RCC->AHB1ENR |= AHB1_EN_MASK;
RCC->AHB1LPENR |= AHB1_LPEN_MASK; RCC->AHB1LPENR |= AHB1_LPEN_MASK;

6
os/hal/platforms/STM32/USBv1/usb_lld.c
View File

@ -330,7 +330,7 @@ void usb_lld_start(USBDriver *usbp) {
#if STM32_USB_USE_USB1 #if STM32_USB_USE_USB1
if (&USBD1 == usbp) { if (&USBD1 == usbp) {
/* USB clock enabled.*/ /* USB clock enabled.*/
RCC->APB1ENR |= RCC_APB1ENR_USBEN; rccEnableUSB(FALSE);
/* Powers up the transceiver while holding the USB in reset state.*/ /* Powers up the transceiver while holding the USB in reset state.*/
STM32_USB->CNTR = CNTR_FRES; STM32_USB->CNTR = CNTR_FRES;
/* Enabling the USB IRQ vectors, this also gives enough time to allow /* Enabling the USB IRQ vectors, this also gives enough time to allow
@ -360,12 +360,12 @@ void usb_lld_stop(USBDriver *usbp) {
/* If in ready state then disables the USB clock.*/ /* If in ready state then disables the USB clock.*/
if (usbp->state == USB_STOP) { if (usbp->state == USB_STOP) {
#if STM32_ADC_USE_ADC1 #if STM32_USB_USE_USB1
if (&USBD1 == usbp) { if (&USBD1 == usbp) {
NVICDisableVector(19); NVICDisableVector(19);
NVICDisableVector(20); NVICDisableVector(20);
STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
RCC->APB1ENR &= ~RCC_APB1ENR_USBEN; rccDisableUSB(FALSE);
} }
#endif #endif
} }

4
os/hal/platforms/STM32/can_lld.c
View File

@ -192,7 +192,7 @@ void can_lld_start(CANDriver *canp) {
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
NVICEnableVector(CAN1_SCE_IRQn, NVICEnableVector(CAN1_SCE_IRQn,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; rccEnableCAN1(FALSE);
} }
#endif #endif
@ -276,7 +276,7 @@ void can_lld_stop(CANDriver *canp) {
NVICDisableVector(USB_LP_CAN1_RX0_IRQn); NVICDisableVector(USB_LP_CAN1_RX0_IRQn);
NVICDisableVector(CAN1_RX1_IRQn); NVICDisableVector(CAN1_RX1_IRQn);
NVICDisableVector(CAN1_SCE_IRQn); NVICDisableVector(CAN1_SCE_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_CAN1EN; rccDisableCAN1(FALSE);
} }
#endif #endif
} }

42
os/hal/platforms/STM32/gpt_lld.c
View File

@ -268,9 +268,8 @@ void gpt_lld_start(GPTDriver *gptp) {
/* Clock activation.*/ /* Clock activation.*/
#if STM32_GPT_USE_TIM1 #if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; rccEnableTIM1(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; rccResetTIM1();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM1_UP_IRQn, NVICEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2; gptp->clock = STM32_TIMCLK2;
@ -278,9 +277,8 @@ void gpt_lld_start(GPTDriver *gptp) {
#endif #endif
#if STM32_GPT_USE_TIM2 #if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; rccEnableTIM2(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; rccResetTIM2();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM2_IRQn, NVICEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
@ -288,9 +286,8 @@ void gpt_lld_start(GPTDriver *gptp) {
#endif #endif
#if STM32_GPT_USE_TIM3 #if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; rccEnableTIM3(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; rccResetTIM3();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM3_IRQn, NVICEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
@ -298,9 +295,8 @@ void gpt_lld_start(GPTDriver *gptp) {
#endif #endif
#if STM32_GPT_USE_TIM4 #if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; rccEnableTIM4(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; rccResetTIM4();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM4_IRQn, NVICEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
@ -309,9 +305,8 @@ void gpt_lld_start(GPTDriver *gptp) {
#if STM32_GPT_USE_TIM5 #if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) { if (&GPTD5 == gptp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; rccEnableTIM5(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; rccResetTIM5();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM5_IRQn, NVICEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1; gptp->clock = STM32_TIMCLK1;
@ -320,9 +315,8 @@ void gpt_lld_start(GPTDriver *gptp) {
#if STM32_GPT_USE_TIM8 #if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) { if (&GPTD8 == gptp) {
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; rccEnableTIM8(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; rccResetTIM8();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM8_UP_IRQn, NVICEnableVector(TIM8_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2; gptp->clock = STM32_TIMCLK2;
@ -359,37 +353,37 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if STM32_GPT_USE_TIM1 #if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
NVICDisableVector(TIM1_UP_IRQn); NVICDisableVector(TIM1_UP_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM2 #if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) { if (&GPTD2 == gptp) {
NVICDisableVector(TIM2_IRQn); NVICDisableVector(TIM2_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM3 #if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) { if (&GPTD3 == gptp) {
NVICDisableVector(TIM3_IRQn); NVICDisableVector(TIM3_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM4 #if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) { if (&GPTD4 == gptp) {
NVICDisableVector(TIM4_IRQn); NVICDisableVector(TIM4_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM5 #if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) { if (&GPTD5 == gptp) {
NVICDisableVector(TIM5_IRQn); NVICDisableVector(TIM5_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; rccDisableTIM5(FALSE);
} }
#endif #endif
#if STM32_GPT_USE_TIM8 #if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) { if (&GPTD8 == gptp) {
NVICDisableVector(TIM8_UP_IRQn); NVICDisableVector(TIM8_UP_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; rccDisableTIM8(FALSE);
} }
#endif #endif
} }

15
os/hal/platforms/STM32/i2c_lld.c
View File

@ -497,8 +497,6 @@ CH_IRQ_HANDLER(VectorC8) {
void i2c_lld_init(void) { void i2c_lld_init(void) {
#if STM32_I2C_USE_I2C1 #if STM32_I2C_USE_I2C1
RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */
RCC->APB1RSTR = 0;
i2cObjectInit(&I2CD1); i2cObjectInit(&I2CD1);
I2CD1.id_i2c = I2C1; I2CD1.id_i2c = I2C1;
@ -512,8 +510,6 @@ void i2c_lld_init(void) {
#endif /* STM32_I2C_USE_I2C */ #endif /* STM32_I2C_USE_I2C */
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; /* reset I2C 2 */
RCC->APB1RSTR = 0;
i2cObjectInit(&I2CD2); i2cObjectInit(&I2CD2);
I2CD2.id_i2c = I2C2; I2CD2.id_i2c = I2C2;
@ -542,7 +538,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* I2C_SUPPORTS_CALLBACKS */
NVICEnableVector(I2C1_ER_IRQn, NVICEnableVector(I2C1_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; /* I2C 1 clock enable */ rccEnableI2C1(FALSE);
} }
#endif #endif
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
@ -553,7 +549,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* I2C_SUPPORTS_CALLBACKS */
NVICEnableVector(I2C2_ER_IRQn, NVICEnableVector(I2C2_ER_IRQn,
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; /* I2C 2 clock enable */ rccEnableI2C2(FALSE);
} }
#endif #endif
} }
@ -569,8 +565,7 @@ void i2c_lld_reset(I2CDriver *i2cp){
chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY),
"i2c_lld_reset: invalid state"); "i2c_lld_reset: invalid state");
RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */ rccResetI2C1();
RCC->APB1RSTR = 0;
} }
@ -699,14 +694,14 @@ void i2c_lld_stop(I2CDriver *i2cp) {
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
NVICDisableVector(I2C1_EV_IRQn); NVICDisableVector(I2C1_EV_IRQn);
NVICDisableVector(I2C1_ER_IRQn); NVICDisableVector(I2C1_ER_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; rccDisableI2C1(FALSE);
} }
#endif #endif
#if STM32_I2C_USE_I2C2 #if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) { if (&I2CD2 == i2cp) {
NVICDisableVector(I2C2_EV_IRQn); NVICDisableVector(I2C2_EV_IRQn);
NVICDisableVector(I2C2_ER_IRQn); NVICDisableVector(I2C2_ER_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN; rccDisableI2C2(FALSE);
} }
#endif #endif
} }

42
os/hal/platforms/STM32/icu_lld.c
View File

@ -287,9 +287,8 @@ void icu_lld_start(ICUDriver *icup) {
/* Clock activation and timer reset.*/ /* Clock activation and timer reset.*/
#if STM32_ICU_USE_TIM1 #if STM32_ICU_USE_TIM1
if (&ICUD1 == icup) { if (&ICUD1 == icup) {
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; rccEnableTIM1(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; rccResetTIM1();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM1_CC_IRQn, NVICEnableVector(TIM1_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
clock = STM32_TIMCLK2; clock = STM32_TIMCLK2;
@ -297,9 +296,8 @@ void icu_lld_start(ICUDriver *icup) {
#endif #endif
#if STM32_ICU_USE_TIM2 #if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) { if (&ICUD2 == icup) {
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; rccEnableTIM2(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; rccResetTIM2();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM2_IRQn, NVICEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -307,9 +305,8 @@ void icu_lld_start(ICUDriver *icup) {
#endif #endif
#if STM32_ICU_USE_TIM3 #if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) { if (&ICUD3 == icup) {
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; rccEnableTIM3(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; rccResetTIM3();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM3_IRQn, NVICEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -317,9 +314,8 @@ void icu_lld_start(ICUDriver *icup) {
#endif #endif
#if STM32_ICU_USE_TIM4 #if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) { if (&ICUD4 == icup) {
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; rccEnableTIM4(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; rccResetTIM4();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM4_IRQn, NVICEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -328,9 +324,8 @@ void icu_lld_start(ICUDriver *icup) {
#if STM32_ICU_USE_TIM5 #if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) { if (&ICUD5 == icup) {
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; rccEnableTIM5(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; rccResetTIM5();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM5_IRQn, NVICEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -338,9 +333,8 @@ void icu_lld_start(ICUDriver *icup) {
#endif #endif
#if STM32_ICU_USE_TIM8 #if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) { if (&ICUD8 == icup) {
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; rccEnableTIM5(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; rccResetTIM5();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM8_CC_IRQn, NVICEnableVector(TIM8_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
clock = STM32_TIMCLK2; clock = STM32_TIMCLK2;
@ -402,38 +396,38 @@ void icu_lld_stop(ICUDriver *icup) {
#if STM32_ICU_USE_TIM1 #if STM32_ICU_USE_TIM1
if (&ICUD1 == icup) { if (&ICUD1 == icup) {
NVICDisableVector(TIM1_CC_IRQn); NVICDisableVector(TIM1_CC_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM2 #if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) { if (&ICUD2 == icup) {
NVICDisableVector(TIM2_IRQn); NVICDisableVector(TIM2_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM3 #if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) { if (&ICUD3 == icup) {
NVICDisableVector(TIM3_IRQn); NVICDisableVector(TIM3_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM4 #if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) { if (&ICUD4 == icup) {
NVICDisableVector(TIM4_IRQn); NVICDisableVector(TIM4_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_ICU_USE_TIM5 #if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) { if (&ICUD5 == icup) {
NVICDisableVector(TIM5_IRQn); NVICDisableVector(TIM5_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; rccDisableTIM5(FALSE);
} }
#endif #endif
} }
#if STM32_ICU_USE_TIM8 #if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) { if (&ICUD8 == icup) {
NVICDisableVector(TIM8_CC_IRQn); NVICDisableVector(TIM8_CC_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; rccDisableTIM8(FALSE);
} }
#endif #endif
} }

19
os/hal/platforms/STM32/mac_lld.c
View File

@ -159,13 +159,10 @@ void mac_lld_init(void) {
} }
/* MAC clocks activation.*/ /* MAC clocks activation.*/
RCC->AHBENR |= RCC_AHBENR_ETHMACEN | rccEnableETH(FALSE);
RCC_AHBENR_ETHMACTXEN |
RCC_AHBENR_ETHMACRXEN;
/* Reset of the MAC core.*/ /* Reset of the MAC core.*/
RCC->AHBRSTR = RCC_AHBRSTR_ETHMACRST; rccResetETH();
RCC->AHBRSTR = 0;
/* Find PHY address.*/ /* Find PHY address.*/
mii_find_phy(); mii_find_phy();
@ -184,9 +181,7 @@ void mac_lld_init(void) {
mii_write_phy(MII_BMCR, BMCR_PDOWN); mii_write_phy(MII_BMCR, BMCR_PDOWN);
/* MAC clocks stopped again.*/ /* MAC clocks stopped again.*/
RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | rccDisableETH(FALSE);
RCC_AHBENR_ETHMACTXEN |
RCC_AHBENR_ETHMACRXEN);
} }
/** /**
@ -208,9 +203,7 @@ void mac_lld_start(MACDriver *macp) {
txptr = (stm32_eth_tx_descriptor_t *)td; txptr = (stm32_eth_tx_descriptor_t *)td;
/* MAC clocks activation.*/ /* MAC clocks activation.*/
RCC->AHBENR |= RCC_AHBENR_ETHMACEN | rccEnableETH(FALSE);
RCC_AHBENR_ETHMACTXEN |
RCC_AHBENR_ETHMACRXEN;
/* Descriptor chains pointers.*/ /* Descriptor chains pointers.*/
ETH->DMARDLAR = (uint32_t)rd; ETH->DMARDLAR = (uint32_t)rd;
@ -241,9 +234,7 @@ void mac_lld_start(MACDriver *macp) {
void mac_lld_stop(MACDriver *macp) { void mac_lld_stop(MACDriver *macp) {
/* MAC clocks stopped.*/ /* MAC clocks stopped.*/
RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | rccDisableETH(FALSE);
RCC_AHBENR_ETHMACTXEN |
RCC_AHBENR_ETHMACRXEN);
} }
/** /**

42
os/hal/platforms/STM32/pwm_lld.c
View File

@ -348,9 +348,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
/* Clock activation and timer reset.*/ /* Clock activation and timer reset.*/
#if STM32_PWM_USE_TIM1 #if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) { if (&PWMD1 == pwmp) {
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; rccEnableTIM1(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; rccResetTIM1();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM1_UP_IRQn, NVICEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
NVICEnableVector(TIM1_CC_IRQn, NVICEnableVector(TIM1_CC_IRQn,
@ -360,9 +359,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif #endif
#if STM32_PWM_USE_TIM2 #if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) { if (&PWMD2 == pwmp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; rccEnableTIM2(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; rccResetTIM2();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM2_IRQn, NVICEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -370,9 +368,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif #endif
#if STM32_PWM_USE_TIM3 #if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) { if (&PWMD3 == pwmp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; rccEnableTIM3(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; rccResetTIM3();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM3_IRQn, NVICEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -380,9 +377,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif #endif
#if STM32_PWM_USE_TIM4 #if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) { if (&PWMD4 == pwmp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; rccEnableTIM4(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; rccResetTIM4();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM4_IRQn, NVICEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -391,9 +387,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#if STM32_PWM_USE_TIM5 #if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) { if (&PWMD5 == pwmp) {
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; rccEnableTIM5(FALSE);
RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; rccResetTIM5();
RCC->APB1RSTR = 0;
NVICEnableVector(TIM5_IRQn, NVICEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
clock = STM32_TIMCLK1; clock = STM32_TIMCLK1;
@ -401,9 +396,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif #endif
#if STM32_PWM_USE_TIM8 #if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) { if (&PWMD8 == pwmp) {
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; rccEnableTIM8(FALSE);
RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; rccResetTIM8();
RCC->APB2RSTR = 0;
NVICEnableVector(TIM8_UP_IRQn, NVICEnableVector(TIM8_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
NVICEnableVector(TIM8_CC_IRQn, NVICEnableVector(TIM8_CC_IRQn,
@ -552,38 +546,38 @@ void pwm_lld_stop(PWMDriver *pwmp) {
if (&PWMD1 == pwmp) { if (&PWMD1 == pwmp) {
NVICDisableVector(TIM1_UP_IRQn); NVICDisableVector(TIM1_UP_IRQn);
NVICDisableVector(TIM1_CC_IRQn); NVICDisableVector(TIM1_CC_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; rccDisableTIM1(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM2 #if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) { if (&PWMD2 == pwmp) {
NVICDisableVector(TIM2_IRQn); NVICDisableVector(TIM2_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; rccDisableTIM2(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM3 #if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) { if (&PWMD3 == pwmp) {
NVICDisableVector(TIM3_IRQn); NVICDisableVector(TIM3_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; rccDisableTIM3(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM4 #if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) { if (&PWMD4 == pwmp) {
NVICDisableVector(TIM4_IRQn); NVICDisableVector(TIM4_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; rccDisableTIM4(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM5 #if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) { if (&PWMD5 == pwmp) {
NVICDisableVector(TIM5_IRQn); NVICDisableVector(TIM5_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; rccDisableTIM5(FALSE);
} }
#endif #endif
#if STM32_PWM_USE_TIM8 #if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) { if (&PWMD8 == pwmp) {
NVICDisableVector(TIM8_UP_IRQn); NVICDisableVector(TIM8_UP_IRQn);
NVICDisableVector(TIM8_CC_IRQn); NVICDisableVector(TIM8_CC_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; rccDisableTIM8(FALSE);
} }
#endif #endif
} }

3
os/hal/platforms/STM32/sdc_lld.c
View File

@ -443,7 +443,7 @@ void sdc_lld_start(SDCDriver *sdcp) {
dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO);
NVICEnableVector(SDIO_IRQn, NVICEnableVector(SDIO_IRQn,
CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
RCC->AHBENR |= RCC_AHBENR_SDIOEN; rccEnableSDIO(FALSE);
} }
/* Configuration, card clock is initially stopped.*/ /* Configuration, card clock is initially stopped.*/
SDIO->POWER = 0; SDIO->POWER = 0;
@ -470,6 +470,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
/* Clock deactivation.*/ /* Clock deactivation.*/
NVICDisableVector(SDIO_IRQn); NVICDisableVector(SDIO_IRQn);
dmaStreamRelease(STM32_DMA2_STREAM4); dmaStreamRelease(STM32_DMA2_STREAM4);
rccDisableSDIO(FALSE);
} }
} }

20
os/hal/platforms/STM32/serial_lld.c
View File

@ -376,35 +376,35 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (sdp->state == SD_STOP) { if (sdp->state == SD_STOP) {
#if STM32_SERIAL_USE_USART1 #if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) { if (&SD1 == sdp) {
RCC->APB2ENR |= RCC_APB2ENR_USART1EN; rccEnableUSART1(FALSE);
NVICEnableVector(USART1_IRQn, NVICEnableVector(USART1_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_USART2 #if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD2 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_USART2EN; rccEnableUSART2(FALSE);
NVICEnableVector(USART2_IRQn, NVICEnableVector(USART2_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_USART3 #if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) { if (&SD3 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_USART3EN; rccEnableUSART3(FALSE);
NVICEnableVector(USART3_IRQn, NVICEnableVector(USART3_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_UART4 #if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_UART4EN; rccEnableUART4(FALSE);
NVICEnableVector(UART4_IRQn, NVICEnableVector(UART4_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
} }
#endif #endif
#if STM32_SERIAL_USE_UART5 #if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) { if (&SD5 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_UART5EN; rccEnableUART5(FALSE);
NVICEnableVector(UART5_IRQn, NVICEnableVector(UART5_IRQn,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
} }
@ -428,35 +428,35 @@ void sd_lld_stop(SerialDriver *sdp) {
usart_deinit(sdp->usart); usart_deinit(sdp->usart);
#if STM32_SERIAL_USE_USART1 #if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) { if (&SD1 == sdp) {
RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; rccDisableUSART1(FALSE);
NVICDisableVector(USART1_IRQn); NVICDisableVector(USART1_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_USART2 #if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD2 == sdp) {
RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; rccDisableUSART2(FALSE);
NVICDisableVector(USART2_IRQn); NVICDisableVector(USART2_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_USART3 #if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) { if (&SD3 == sdp) {
RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; rccDisableUSART3(FALSE);
NVICDisableVector(USART3_IRQn); NVICDisableVector(USART3_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_UART4 #if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN; rccDisableUART4(FALSE);
NVICDisableVector(UART4_IRQn); NVICDisableVector(UART4_IRQn);
return; return;
} }
#endif #endif
#if STM32_SERIAL_USE_UART5 #if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) { if (&SD5 == sdp) {
RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN; rccDisableUART5(FALSE);
NVICDisableVector(UART5_IRQn); NVICDisableVector(UART5_IRQn);
return; return;
} }

12
os/hal/platforms/STM32/spi_lld.c
View File

@ -192,7 +192,7 @@ void spi_lld_start(SPIDriver *spip) {
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; rccEnableSPI1(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI2 #if STM32_SPI_USE_SPI2
@ -208,7 +208,7 @@ void spi_lld_start(SPIDriver *spip) {
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; rccEnableSPI2(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI3 #if STM32_SPI_USE_SPI3
@ -224,7 +224,7 @@ void spi_lld_start(SPIDriver *spip) {
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip); (void *)spip);
chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; rccEnableSPI3(FALSE);
} }
#endif #endif
@ -272,21 +272,21 @@ void spi_lld_stop(SPIDriver *spip) {
if (&SPID1 == spip) { if (&SPID1 == spip) {
dmaStreamRelease(STM32_DMA1_STREAM2); dmaStreamRelease(STM32_DMA1_STREAM2);
dmaStreamRelease(STM32_DMA1_STREAM3); dmaStreamRelease(STM32_DMA1_STREAM3);
RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; rccDisableSPI1(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI2 #if STM32_SPI_USE_SPI2
if (&SPID2 == spip) { if (&SPID2 == spip) {
dmaStreamRelease(STM32_DMA1_STREAM4); dmaStreamRelease(STM32_DMA1_STREAM4);
dmaStreamRelease(STM32_DMA1_STREAM5); dmaStreamRelease(STM32_DMA1_STREAM5);
RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; rccDisableSPI2(FALSE);
} }
#endif #endif
#if STM32_SPI_USE_SPI3 #if STM32_SPI_USE_SPI3
if (&SPID3 == spip) { if (&SPID3 == spip) {
dmaStreamRelease(STM32_DMA1_STREAM1); dmaStreamRelease(STM32_DMA1_STREAM1);
dmaStreamRelease(STM32_DMA1_STREAM2); dmaStreamRelease(STM32_DMA1_STREAM2);
RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; rccDisableSPI3(FALSE);
} }
#endif #endif
} }

12
os/hal/platforms/STM32/uart_lld.c
View File

@ -362,7 +362,7 @@ void uart_lld_start(UARTDriver *uartp) {
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
RCC->APB2ENR |= RCC_APB2ENR_USART1EN; rccEnableUSART1(FALSE);
NVICEnableVector(USART1_IRQn, NVICEnableVector(USART1_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
} }
@ -381,7 +381,7 @@ void uart_lld_start(UARTDriver *uartp) {
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
RCC->APB1ENR |= RCC_APB1ENR_USART2EN; rccEnableUSART2(FALSE);
NVICEnableVector(USART2_IRQn, NVICEnableVector(USART2_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
} }
@ -400,7 +400,7 @@ void uart_lld_start(UARTDriver *uartp) {
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp); (void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
RCC->APB1ENR |= RCC_APB1ENR_USART3EN; rccEnableUSART3(FALSE);
NVICEnableVector(USART3_IRQn, NVICEnableVector(USART3_IRQn,
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
} }
@ -438,7 +438,7 @@ void uart_lld_stop(UARTDriver *uartp) {
dmaStreamRelease(STM32_DMA1_STREAM4); dmaStreamRelease(STM32_DMA1_STREAM4);
dmaStreamRelease(STM32_DMA1_STREAM5); dmaStreamRelease(STM32_DMA1_STREAM5);
NVICDisableVector(USART1_IRQn); NVICDisableVector(USART1_IRQn);
RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; rccDisableUSART1(FALSE);
return; return;
} }
#endif #endif
@ -448,7 +448,7 @@ void uart_lld_stop(UARTDriver *uartp) {
dmaStreamRelease(STM32_DMA1_STREAM6); dmaStreamRelease(STM32_DMA1_STREAM6);
dmaStreamRelease(STM32_DMA1_STREAM7); dmaStreamRelease(STM32_DMA1_STREAM7);
NVICDisableVector(USART2_IRQn); NVICDisableVector(USART2_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; rccDisableUSART2(FALSE);
return; return;
} }
#endif #endif
@ -458,7 +458,7 @@ void uart_lld_stop(UARTDriver *uartp) {
dmaStreamRelease(STM32_DMA1_STREAM2); dmaStreamRelease(STM32_DMA1_STREAM2);
dmaStreamRelease(STM32_DMA1_STREAM3); dmaStreamRelease(STM32_DMA1_STREAM3);
NVICDisableVector(USART3_IRQn); NVICDisableVector(USART3_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; rccDisableUSART3(FALSE);
return; return;
} }
#endif #endif

8
os/hal/platforms/STM32F1xx/adc_lld.c
View File

@ -100,7 +100,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; STM32_DMA_CR_TEIE | STM32_DMA_CR_EN;
/* Temporary activation.*/ /* Temporary activation.*/
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; rccEnableADC1(FALSE);
ADC1->CR1 = 0; ADC1->CR1 = 0;
ADC1->CR2 = ADC_CR2_ADON; ADC1->CR2 = ADC_CR2_ADON;
@ -116,7 +116,7 @@ void adc_lld_init(void) {
/* Return the ADC in low power mode.*/ /* Return the ADC in low power mode.*/
ADC1->CR2 = 0; ADC1->CR2 = 0;
RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; rccDisableADC1(FALSE);
#endif #endif
} }
@ -140,7 +140,7 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp); (void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; rccEnableADC1(FALSE);
} }
#endif #endif
@ -167,7 +167,7 @@ void adc_lld_stop(ADCDriver *adcp) {
ADC1->CR1 = 0; ADC1->CR1 = 0;
ADC1->CR2 = 0; ADC1->CR2 = 0;
dmaStreamRelease(adcp->dmastp); dmaStreamRelease(adcp->dmastp);
RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; rccDisableADC1(FALSE);
} }
#endif #endif
} }

6
os/hal/platforms/STM32F1xx/hal_lld.c
View File

@ -59,10 +59,8 @@
void hal_lld_init(void) { void hal_lld_init(void) {
/* Reset of all peripherals.*/ /* Reset of all peripherals.*/
RCC->APB1RSTR = 0xFFFFFFFF; rccResetAPB1(0xFFFFFFFF);
RCC->APB2RSTR = 0xFFFFFFFF; rccResetAPB2(0xFFFFFFFF);
RCC->APB1RSTR = 0;
RCC->APB2RSTR = 0;
/* SysTick initialization using the system clock.*/ /* SysTick initialization using the system clock.*/
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

3
os/hal/platforms/STM32F1xx/hal_lld.h
View File

@ -578,8 +578,9 @@
#define FALSE 0 #define FALSE 0
#define TRUE (!FALSE) #define TRUE (!FALSE)
/* STM32 DMA support code.*/ /* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

3
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -787,8 +787,9 @@
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
/* STM32 DMA support code.*/ /* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

3
readme.txt
View File

@ -97,6 +97,9 @@
drivers. drivers.
(uIP demo to be adapted) (uIP demo to be adapted)
(implement macStop() in AT91SAM7X implementation) (implement macStop() in AT91SAM7X implementation)
- NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies
the use of the RCC resources and hides most differences found among the
various STM32 sub-families.
- NEW: New DMA helper driver for STM32, it simplifies the use of the DMA - NEW: New DMA helper driver for STM32, it simplifies the use of the DMA
resources and hides most differences with the new enhanced DMA units resources and hides most differences with the new enhanced DMA units
found in the STM32F2xx sub-family. found in the STM32F2xx sub-family.

3
testhal/STM32F1xx/PWM-ICU/Makefile
View File

@ -61,6 +61,9 @@ include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/kernel/kernel.mk
#include $(CHIBIOS)/test/test.mk #include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F103xB.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.
CSRC = $(PORTSRC) \ CSRC = $(PORTSRC) \