git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3320 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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46538d795b
commit
3a94137eb3
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@ -437,10 +437,10 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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/* Enabling DMA clocks required by the current streams set.*/
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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rccEnableDMA1(FALSE);
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#if STM32_HAS_DMA2
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if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
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RCC->AHBENR |= RCC_AHBENR_DMA2EN;
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rccEnableDMA2(FALSE);
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#endif
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/* Putting the stream in a safe state.*/
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@ -484,10 +484,10 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
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/* Shutting down clocks that are no more required, if any.*/
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
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RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
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rccDisableDMA1(FALSE);
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#if STM32_HAS_DMA2
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if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
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RCC->AHBENR &= ~RCC_AHBENR_DMA2EN;
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rccDisableDMA2(FALSE);
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#endif
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}
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@ -79,7 +79,7 @@ void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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RCC->APB2ENR |= APB2_EN_MASK;
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rccEnableAPB2(APB2_EN_MASK, FALSE);
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/*
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* Initial GPIO setup.
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@ -35,7 +35,6 @@
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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#define AHB_LPEN_MASK AHB_EN_MASK
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#elif defined(STM32F2XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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@ -92,8 +91,7 @@ void _pal_lld_init(const PALConfig *config) {
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* Enables the GPIO related clocks.
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*/
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#if defined(STM32L1XX_MD)
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RCC->AHBENR |= AHB_EN_MASK;
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RCC->AHBLPENR |= AHB_LPEN_MASK;
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rccEnableAHB(AHB_EN_MASK, TRUE);
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#elif defined(STM32F2XX)
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RCC->AHB1ENR |= AHB1_EN_MASK;
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RCC->AHB1LPENR |= AHB1_LPEN_MASK;
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@ -330,7 +330,7 @@ void usb_lld_start(USBDriver *usbp) {
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#if STM32_USB_USE_USB1
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if (&USBD1 == usbp) {
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/* USB clock enabled.*/
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RCC->APB1ENR |= RCC_APB1ENR_USBEN;
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rccEnableUSB(FALSE);
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/* Powers up the transceiver while holding the USB in reset state.*/
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STM32_USB->CNTR = CNTR_FRES;
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/* Enabling the USB IRQ vectors, this also gives enough time to allow
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@ -360,12 +360,12 @@ void usb_lld_stop(USBDriver *usbp) {
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/* If in ready state then disables the USB clock.*/
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if (usbp->state == USB_STOP) {
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#if STM32_ADC_USE_ADC1
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#if STM32_USB_USE_USB1
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if (&USBD1 == usbp) {
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NVICDisableVector(19);
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NVICDisableVector(20);
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STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
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RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
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rccDisableUSB(FALSE);
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}
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#endif
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}
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@ -192,7 +192,7 @@ void can_lld_start(CANDriver *canp) {
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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NVICEnableVector(CAN1_SCE_IRQn,
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
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rccEnableCAN1(FALSE);
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}
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#endif
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@ -276,7 +276,7 @@ void can_lld_stop(CANDriver *canp) {
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NVICDisableVector(USB_LP_CAN1_RX0_IRQn);
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NVICDisableVector(CAN1_RX1_IRQn);
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NVICDisableVector(CAN1_SCE_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_CAN1EN;
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rccDisableCAN1(FALSE);
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}
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#endif
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}
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@ -268,9 +268,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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/* Clock activation.*/
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#if STM32_GPT_USE_TIM1
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if (&GPTD1 == gptp) {
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
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RCC->APB2RSTR = 0;
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rccEnableTIM1(FALSE);
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rccResetTIM1();
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NVICEnableVector(TIM1_UP_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK2;
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@ -278,9 +277,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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#endif
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#if STM32_GPT_USE_TIM2
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if (&GPTD2 == gptp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM2(FALSE);
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rccResetTIM2();
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NVICEnableVector(TIM2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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@ -288,9 +286,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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#endif
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#if STM32_GPT_USE_TIM3
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if (&GPTD3 == gptp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM3(FALSE);
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rccResetTIM3();
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NVICEnableVector(TIM3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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@ -298,9 +295,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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#endif
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#if STM32_GPT_USE_TIM4
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if (&GPTD4 == gptp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM4(FALSE);
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rccResetTIM4();
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NVICEnableVector(TIM4_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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@ -309,9 +305,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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#if STM32_GPT_USE_TIM5
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if (&GPTD5 == gptp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM5(FALSE);
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rccResetTIM5();
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NVICEnableVector(TIM5_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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@ -320,9 +315,8 @@ void gpt_lld_start(GPTDriver *gptp) {
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#if STM32_GPT_USE_TIM8
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if (&GPTD8 == gptp) {
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RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
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RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST;
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RCC->APB2RSTR = 0;
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rccEnableTIM8(FALSE);
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rccResetTIM8();
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NVICEnableVector(TIM8_UP_IRQn,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK2;
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@ -359,37 +353,37 @@ void gpt_lld_stop(GPTDriver *gptp) {
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#if STM32_GPT_USE_TIM1
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if (&GPTD1 == gptp) {
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NVICDisableVector(TIM1_UP_IRQn);
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
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rccDisableTIM1(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM2
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if (&GPTD2 == gptp) {
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NVICDisableVector(TIM2_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
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rccDisableTIM2(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM3
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if (&GPTD3 == gptp) {
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NVICDisableVector(TIM3_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
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rccDisableTIM3(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM4
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if (&GPTD4 == gptp) {
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NVICDisableVector(TIM4_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
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rccDisableTIM4(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM5
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if (&GPTD5 == gptp) {
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NVICDisableVector(TIM5_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
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rccDisableTIM5(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM8
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if (&GPTD8 == gptp) {
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NVICDisableVector(TIM8_UP_IRQn);
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN;
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rccDisableTIM8(FALSE);
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}
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#endif
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}
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@ -497,8 +497,6 @@ CH_IRQ_HANDLER(VectorC8) {
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void i2c_lld_init(void) {
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#if STM32_I2C_USE_I2C1
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RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */
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RCC->APB1RSTR = 0;
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i2cObjectInit(&I2CD1);
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I2CD1.id_i2c = I2C1;
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@ -512,8 +510,6 @@ void i2c_lld_init(void) {
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#endif /* STM32_I2C_USE_I2C */
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#if STM32_I2C_USE_I2C2
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RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; /* reset I2C 2 */
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RCC->APB1RSTR = 0;
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i2cObjectInit(&I2CD2);
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I2CD2.id_i2c = I2C2;
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@ -542,7 +538,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
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#endif /* I2C_SUPPORTS_CALLBACKS */
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NVICEnableVector(I2C1_ER_IRQn,
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CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; /* I2C 1 clock enable */
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rccEnableI2C1(FALSE);
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}
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#endif
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#if STM32_I2C_USE_I2C2
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@ -553,7 +549,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
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#endif /* I2C_SUPPORTS_CALLBACKS */
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NVICEnableVector(I2C2_ER_IRQn,
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CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
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RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; /* I2C 2 clock enable */
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rccEnableI2C2(FALSE);
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}
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#endif
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}
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@ -569,8 +565,7 @@ void i2c_lld_reset(I2CDriver *i2cp){
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chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY),
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"i2c_lld_reset: invalid state");
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RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */
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RCC->APB1RSTR = 0;
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rccResetI2C1();
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}
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@ -699,14 +694,14 @@ void i2c_lld_stop(I2CDriver *i2cp) {
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if (&I2CD1 == i2cp) {
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NVICDisableVector(I2C1_EV_IRQn);
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NVICDisableVector(I2C1_ER_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
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rccDisableI2C1(FALSE);
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}
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#endif
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#if STM32_I2C_USE_I2C2
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if (&I2CD2 == i2cp) {
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NVICDisableVector(I2C2_EV_IRQn);
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NVICDisableVector(I2C2_ER_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
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rccDisableI2C2(FALSE);
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}
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#endif
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}
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@ -287,9 +287,8 @@ void icu_lld_start(ICUDriver *icup) {
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/* Clock activation and timer reset.*/
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#if STM32_ICU_USE_TIM1
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if (&ICUD1 == icup) {
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
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RCC->APB2RSTR = 0;
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rccEnableTIM1(FALSE);
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rccResetTIM1();
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NVICEnableVector(TIM1_CC_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
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clock = STM32_TIMCLK2;
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@ -297,9 +296,8 @@ void icu_lld_start(ICUDriver *icup) {
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#endif
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#if STM32_ICU_USE_TIM2
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if (&ICUD2 == icup) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM2(FALSE);
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rccResetTIM2();
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NVICEnableVector(TIM2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
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clock = STM32_TIMCLK1;
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@ -307,9 +305,8 @@ void icu_lld_start(ICUDriver *icup) {
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#endif
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#if STM32_ICU_USE_TIM3
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if (&ICUD3 == icup) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM3(FALSE);
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rccResetTIM3();
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NVICEnableVector(TIM3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
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clock = STM32_TIMCLK1;
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@ -317,9 +314,8 @@ void icu_lld_start(ICUDriver *icup) {
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#endif
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#if STM32_ICU_USE_TIM4
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if (&ICUD4 == icup) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM4(FALSE);
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rccResetTIM4();
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NVICEnableVector(TIM4_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
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clock = STM32_TIMCLK1;
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@ -328,9 +324,8 @@ void icu_lld_start(ICUDriver *icup) {
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#if STM32_ICU_USE_TIM5
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if (&ICUD5 == icup) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
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RCC->APB1RSTR = 0;
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rccEnableTIM5(FALSE);
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rccResetTIM5();
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NVICEnableVector(TIM5_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
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clock = STM32_TIMCLK1;
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@ -338,9 +333,8 @@ void icu_lld_start(ICUDriver *icup) {
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#endif
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#if STM32_ICU_USE_TIM8
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if (&ICUD8 == icup) {
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RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
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RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST;
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RCC->APB2RSTR = 0;
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rccEnableTIM5(FALSE);
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rccResetTIM5();
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NVICEnableVector(TIM8_CC_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
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clock = STM32_TIMCLK2;
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@ -402,38 +396,38 @@ void icu_lld_stop(ICUDriver *icup) {
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#if STM32_ICU_USE_TIM1
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if (&ICUD1 == icup) {
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NVICDisableVector(TIM1_CC_IRQn);
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
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rccDisableTIM1(FALSE);
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}
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#endif
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#if STM32_ICU_USE_TIM2
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if (&ICUD2 == icup) {
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NVICDisableVector(TIM2_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
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rccDisableTIM2(FALSE);
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}
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#endif
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#if STM32_ICU_USE_TIM3
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if (&ICUD3 == icup) {
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NVICDisableVector(TIM3_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
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rccDisableTIM3(FALSE);
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}
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#endif
|
||||
#if STM32_ICU_USE_TIM4
|
||||
if (&ICUD4 == icup) {
|
||||
NVICDisableVector(TIM4_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
|
||||
rccDisableTIM4(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_ICU_USE_TIM5
|
||||
if (&ICUD5 == icup) {
|
||||
NVICDisableVector(TIM5_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
|
||||
rccDisableTIM5(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if STM32_ICU_USE_TIM8
|
||||
if (&ICUD8 == icup) {
|
||||
NVICDisableVector(TIM8_CC_IRQn);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN;
|
||||
rccDisableTIM8(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -159,13 +159,10 @@ void mac_lld_init(void) {
|
|||
}
|
||||
|
||||
/* MAC clocks activation.*/
|
||||
RCC->AHBENR |= RCC_AHBENR_ETHMACEN |
|
||||
RCC_AHBENR_ETHMACTXEN |
|
||||
RCC_AHBENR_ETHMACRXEN;
|
||||
rccEnableETH(FALSE);
|
||||
|
||||
/* Reset of the MAC core.*/
|
||||
RCC->AHBRSTR = RCC_AHBRSTR_ETHMACRST;
|
||||
RCC->AHBRSTR = 0;
|
||||
rccResetETH();
|
||||
|
||||
/* Find PHY address.*/
|
||||
mii_find_phy();
|
||||
|
@ -184,9 +181,7 @@ void mac_lld_init(void) {
|
|||
mii_write_phy(MII_BMCR, BMCR_PDOWN);
|
||||
|
||||
/* MAC clocks stopped again.*/
|
||||
RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN |
|
||||
RCC_AHBENR_ETHMACTXEN |
|
||||
RCC_AHBENR_ETHMACRXEN);
|
||||
rccDisableETH(FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -208,9 +203,7 @@ void mac_lld_start(MACDriver *macp) {
|
|||
txptr = (stm32_eth_tx_descriptor_t *)td;
|
||||
|
||||
/* MAC clocks activation.*/
|
||||
RCC->AHBENR |= RCC_AHBENR_ETHMACEN |
|
||||
RCC_AHBENR_ETHMACTXEN |
|
||||
RCC_AHBENR_ETHMACRXEN;
|
||||
rccEnableETH(FALSE);
|
||||
|
||||
/* Descriptor chains pointers.*/
|
||||
ETH->DMARDLAR = (uint32_t)rd;
|
||||
|
@ -241,9 +234,7 @@ void mac_lld_start(MACDriver *macp) {
|
|||
void mac_lld_stop(MACDriver *macp) {
|
||||
|
||||
/* MAC clocks stopped.*/
|
||||
RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN |
|
||||
RCC_AHBENR_ETHMACTXEN |
|
||||
RCC_AHBENR_ETHMACRXEN);
|
||||
rccDisableETH(FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -348,9 +348,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
/* Clock activation and timer reset.*/
|
||||
#if STM32_PWM_USE_TIM1
|
||||
if (&PWMD1 == pwmp) {
|
||||
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
rccEnableTIM1(FALSE);
|
||||
rccResetTIM1();
|
||||
NVICEnableVector(TIM1_UP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
|
||||
NVICEnableVector(TIM1_CC_IRQn,
|
||||
|
@ -360,9 +359,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
#endif
|
||||
#if STM32_PWM_USE_TIM2
|
||||
if (&PWMD2 == pwmp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
|
||||
RCC->APB1RSTR = 0;
|
||||
rccEnableTIM2(FALSE);
|
||||
rccResetTIM2();
|
||||
NVICEnableVector(TIM2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
|
||||
clock = STM32_TIMCLK1;
|
||||
|
@ -370,9 +368,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
#endif
|
||||
#if STM32_PWM_USE_TIM3
|
||||
if (&PWMD3 == pwmp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
|
||||
RCC->APB1RSTR = 0;
|
||||
rccEnableTIM3(FALSE);
|
||||
rccResetTIM3();
|
||||
NVICEnableVector(TIM3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
|
||||
clock = STM32_TIMCLK1;
|
||||
|
@ -380,9 +377,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
#endif
|
||||
#if STM32_PWM_USE_TIM4
|
||||
if (&PWMD4 == pwmp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
|
||||
RCC->APB1RSTR = 0;
|
||||
rccEnableTIM4(FALSE);
|
||||
rccResetTIM4();
|
||||
NVICEnableVector(TIM4_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
|
||||
clock = STM32_TIMCLK1;
|
||||
|
@ -391,9 +387,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
|
||||
#if STM32_PWM_USE_TIM5
|
||||
if (&PWMD5 == pwmp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
|
||||
RCC->APB1RSTR = 0;
|
||||
rccEnableTIM5(FALSE);
|
||||
rccResetTIM5();
|
||||
NVICEnableVector(TIM5_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
|
||||
clock = STM32_TIMCLK1;
|
||||
|
@ -401,9 +396,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
|
|||
#endif
|
||||
#if STM32_PWM_USE_TIM8
|
||||
if (&PWMD8 == pwmp) {
|
||||
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
rccEnableTIM8(FALSE);
|
||||
rccResetTIM8();
|
||||
NVICEnableVector(TIM8_UP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
|
||||
NVICEnableVector(TIM8_CC_IRQn,
|
||||
|
@ -552,38 +546,38 @@ void pwm_lld_stop(PWMDriver *pwmp) {
|
|||
if (&PWMD1 == pwmp) {
|
||||
NVICDisableVector(TIM1_UP_IRQn);
|
||||
NVICDisableVector(TIM1_CC_IRQn);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
|
||||
rccDisableTIM1(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_PWM_USE_TIM2
|
||||
if (&PWMD2 == pwmp) {
|
||||
NVICDisableVector(TIM2_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
|
||||
rccDisableTIM2(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_PWM_USE_TIM3
|
||||
if (&PWMD3 == pwmp) {
|
||||
NVICDisableVector(TIM3_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
|
||||
rccDisableTIM3(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_PWM_USE_TIM4
|
||||
if (&PWMD4 == pwmp) {
|
||||
NVICDisableVector(TIM4_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
|
||||
rccDisableTIM4(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_PWM_USE_TIM5
|
||||
if (&PWMD5 == pwmp) {
|
||||
NVICDisableVector(TIM5_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
|
||||
rccDisableTIM5(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_PWM_USE_TIM8
|
||||
if (&PWMD8 == pwmp) {
|
||||
NVICDisableVector(TIM8_UP_IRQn);
|
||||
NVICDisableVector(TIM8_CC_IRQn);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN;
|
||||
rccDisableTIM8(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -443,7 +443,7 @@ void sdc_lld_start(SDCDriver *sdcp) {
|
|||
dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO);
|
||||
NVICEnableVector(SDIO_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
|
||||
RCC->AHBENR |= RCC_AHBENR_SDIOEN;
|
||||
rccEnableSDIO(FALSE);
|
||||
}
|
||||
/* Configuration, card clock is initially stopped.*/
|
||||
SDIO->POWER = 0;
|
||||
|
@ -470,6 +470,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
|
|||
/* Clock deactivation.*/
|
||||
NVICDisableVector(SDIO_IRQn);
|
||||
dmaStreamRelease(STM32_DMA2_STREAM4);
|
||||
rccDisableSDIO(FALSE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -376,35 +376,35 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
|
|||
if (sdp->state == SD_STOP) {
|
||||
#if STM32_SERIAL_USE_USART1
|
||||
if (&SD1 == sdp) {
|
||||
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
||||
rccEnableUSART1(FALSE);
|
||||
NVICEnableVector(USART1_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_USART2
|
||||
if (&SD2 == sdp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
||||
rccEnableUSART2(FALSE);
|
||||
NVICEnableVector(USART2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_USART3
|
||||
if (&SD3 == sdp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
|
||||
rccEnableUSART3(FALSE);
|
||||
NVICEnableVector(USART3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_UART4
|
||||
if (&SD4 == sdp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
|
||||
rccEnableUART4(FALSE);
|
||||
NVICEnableVector(UART4_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_UART5
|
||||
if (&SD5 == sdp) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_UART5EN;
|
||||
rccEnableUART5(FALSE);
|
||||
NVICEnableVector(UART5_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
|
||||
}
|
||||
|
@ -428,35 +428,35 @@ void sd_lld_stop(SerialDriver *sdp) {
|
|||
usart_deinit(sdp->usart);
|
||||
#if STM32_SERIAL_USE_USART1
|
||||
if (&SD1 == sdp) {
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
|
||||
rccDisableUSART1(FALSE);
|
||||
NVICDisableVector(USART1_IRQn);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_USART2
|
||||
if (&SD2 == sdp) {
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
|
||||
rccDisableUSART2(FALSE);
|
||||
NVICDisableVector(USART2_IRQn);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_USART3
|
||||
if (&SD3 == sdp) {
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
|
||||
rccDisableUSART3(FALSE);
|
||||
NVICDisableVector(USART3_IRQn);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_UART4
|
||||
if (&SD4 == sdp) {
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN;
|
||||
rccDisableUART4(FALSE);
|
||||
NVICDisableVector(UART4_IRQn);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SERIAL_USE_UART5
|
||||
if (&SD5 == sdp) {
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN;
|
||||
rccDisableUART5(FALSE);
|
||||
NVICDisableVector(UART5_IRQn);
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -192,7 +192,7 @@ void spi_lld_start(SPIDriver *spip) {
|
|||
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||
(void *)spip);
|
||||
chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
|
||||
rccEnableSPI1(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI2
|
||||
|
@ -208,7 +208,7 @@ void spi_lld_start(SPIDriver *spip) {
|
|||
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||
(void *)spip);
|
||||
chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
|
||||
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
|
||||
rccEnableSPI2(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI3
|
||||
|
@ -224,7 +224,7 @@ void spi_lld_start(SPIDriver *spip) {
|
|||
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||
(void *)spip);
|
||||
chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
|
||||
RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;
|
||||
rccEnableSPI3(FALSE);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -272,21 +272,21 @@ void spi_lld_stop(SPIDriver *spip) {
|
|||
if (&SPID1 == spip) {
|
||||
dmaStreamRelease(STM32_DMA1_STREAM2);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM3);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
|
||||
rccDisableSPI1(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI2
|
||||
if (&SPID2 == spip) {
|
||||
dmaStreamRelease(STM32_DMA1_STREAM4);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM5);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
|
||||
rccDisableSPI2(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI3
|
||||
if (&SPID3 == spip) {
|
||||
dmaStreamRelease(STM32_DMA1_STREAM1);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM2);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN;
|
||||
rccDisableSPI3(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -362,7 +362,7 @@ void uart_lld_start(UARTDriver *uartp) {
|
|||
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
|
||||
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
||||
rccEnableUSART1(FALSE);
|
||||
NVICEnableVector(USART1_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
|
||||
}
|
||||
|
@ -381,7 +381,7 @@ void uart_lld_start(UARTDriver *uartp) {
|
|||
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
||||
rccEnableUSART2(FALSE);
|
||||
NVICEnableVector(USART2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
|
||||
}
|
||||
|
@ -400,7 +400,7 @@ void uart_lld_start(UARTDriver *uartp) {
|
|||
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
|
||||
rccEnableUSART3(FALSE);
|
||||
NVICEnableVector(USART3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
|
||||
}
|
||||
|
@ -438,7 +438,7 @@ void uart_lld_stop(UARTDriver *uartp) {
|
|||
dmaStreamRelease(STM32_DMA1_STREAM4);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM5);
|
||||
NVICDisableVector(USART1_IRQn);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
|
||||
rccDisableUSART1(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
@ -448,7 +448,7 @@ void uart_lld_stop(UARTDriver *uartp) {
|
|||
dmaStreamRelease(STM32_DMA1_STREAM6);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM7);
|
||||
NVICDisableVector(USART2_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
|
||||
rccDisableUSART2(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
@ -458,7 +458,7 @@ void uart_lld_stop(UARTDriver *uartp) {
|
|||
dmaStreamRelease(STM32_DMA1_STREAM2);
|
||||
dmaStreamRelease(STM32_DMA1_STREAM3);
|
||||
NVICDisableVector(USART3_IRQn);
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
|
||||
rccDisableUSART3(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -100,7 +100,7 @@ void adc_lld_init(void) {
|
|||
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN;
|
||||
|
||||
/* Temporary activation.*/
|
||||
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
|
||||
rccEnableADC1(FALSE);
|
||||
ADC1->CR1 = 0;
|
||||
ADC1->CR2 = ADC_CR2_ADON;
|
||||
|
||||
|
@ -116,7 +116,7 @@ void adc_lld_init(void) {
|
|||
|
||||
/* Return the ADC in low power mode.*/
|
||||
ADC1->CR2 = 0;
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
|
||||
rccDisableADC1(FALSE);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -140,7 +140,7 @@ void adc_lld_start(ADCDriver *adcp) {
|
|||
(void *)adcp);
|
||||
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
|
||||
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
|
||||
rccEnableADC1(FALSE);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -167,7 +167,7 @@ void adc_lld_stop(ADCDriver *adcp) {
|
|||
ADC1->CR1 = 0;
|
||||
ADC1->CR2 = 0;
|
||||
dmaStreamRelease(adcp->dmastp);
|
||||
RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
|
||||
rccDisableADC1(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -59,10 +59,8 @@
|
|||
void hal_lld_init(void) {
|
||||
|
||||
/* Reset of all peripherals.*/
|
||||
RCC->APB1RSTR = 0xFFFFFFFF;
|
||||
RCC->APB2RSTR = 0xFFFFFFFF;
|
||||
RCC->APB1RSTR = 0;
|
||||
RCC->APB2RSTR = 0;
|
||||
rccResetAPB1(0xFFFFFFFF);
|
||||
rccResetAPB2(0xFFFFFFFF);
|
||||
|
||||
/* SysTick initialization using the system clock.*/
|
||||
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
|
||||
|
|
|
@ -578,8 +578,9 @@
|
|||
#define FALSE 0
|
||||
#define TRUE (!FALSE)
|
||||
|
||||
/* STM32 DMA support code.*/
|
||||
/* STM32 DMA and RCC helpers.*/
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
@ -787,8 +787,9 @@
|
|||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* STM32 DMA support code.*/
|
||||
/* STM32 DMA and RCC helpers.*/
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
@ -97,6 +97,9 @@
|
|||
drivers.
|
||||
(uIP demo to be adapted)
|
||||
(implement macStop() in AT91SAM7X implementation)
|
||||
- NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies
|
||||
the use of the RCC resources and hides most differences found among the
|
||||
various STM32 sub-families.
|
||||
- NEW: New DMA helper driver for STM32, it simplifies the use of the DMA
|
||||
resources and hides most differences with the new enhanced DMA units
|
||||
found in the STM32F2xx sub-family.
|
||||
|
|
|
@ -61,6 +61,9 @@ include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
|
|||
include $(CHIBIOS)/os/kernel/kernel.mk
|
||||
#include $(CHIBIOS)/test/test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(PORTLD)/STM32F103xB.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(PORTSRC) \
|
||||
|
|
Loading…
Reference in New Issue