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Improved PLLSAI for STM32F446xx and STM32F469xx/79xx. 

Updated mcuconf.h for STM32F446xx and STM32F469xx/79xx.
Added Clock 48 selector.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9575 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-06-04 16:01:07 +00:00
parent c325b52ac1
commit 3bbaa571d4
5 changed files with 53 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h
View File

@ -45,9 +45,18 @@
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLN_VALUE 360
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SM_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIM_VALUE 4
#define STM32_PLLSAIP_VALUE 8
#define STM32_PLLSAIQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
@ -58,18 +67,9 @@
#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SM_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIM_VALUE 4
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE

22
demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h
View File

@ -45,9 +45,18 @@
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLN_VALUE 360
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SM_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIM_VALUE 4
#define STM32_PLLSAIP_VALUE 8
#define STM32_PLLSAIQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
@ -58,18 +67,9 @@
#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SM_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIM_VALUE 4
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE

14
demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h
View File

@ -48,6 +48,13 @@
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
@ -58,13 +65,6 @@
#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
#define STM32_CK48MSEL STM32_CK48MSEL_PLL

4
os/hal/ports/STM32/STM32F4xx/hal_lld.c
View File

@ -238,8 +238,8 @@ void stm32_clock_init(void) {
#if STM32_ACTIVATE_PLLSAI
/* PLLSAI activation.*/
RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ |
STM32_PLLSAIP;
RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
STM32_PLLSAIQ | STM32_PLLSAIM;
RCC->CR |= RCC_CR_PLLSAION;

24
os/hal/ports/STM32/STM32F4xx/hal_lld.h
View File

@ -838,6 +838,16 @@
#define STM32_PLLSAIN_VALUE 192
#endif
/**
* @brief PLLSAIM value.
* @note The allowed values are 2..63.
* @note The default value is calculated for a 96MHz SAI clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAIM_VALUE 4
#endif
/**
* @brief PLLSAIR value.
* @note The allowed values are 2..7.
@ -851,7 +861,7 @@
* @note The allowed values are 2, 4, 6 and 8.
*/
#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIP_VALUE 8
#endif
/**
@ -1690,6 +1700,16 @@
#define STM32_ACTIVATE_PLLSAI FALSE
#endif
/**
* @brief STM32_PLLSAIM field.
*/
#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
#else
#error "invalid STM32_PLLSAIM_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAIN field.
*/
@ -1917,7 +1937,7 @@
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
#else
#error "invalid source selected for PLL48CLK clock"
#endif