git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5231 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
ef0c3e5738
commit
3c730b6731
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@ -52,11 +52,6 @@ void hal_lld_init(void) {
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extern void _vectors(void);
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extern void _vectors(void);
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uint32_t n;
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uint32_t n;
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/* Enables the branch prediction, clears and enables the BTB into the
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BUCSR special register (1013).*/
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asm volatile ("li %%r3, 0x0201 \t\n"
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"mtspr 1013, %%r3": : : "r3");
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/* FLASH wait states and prefetching setup.*/
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/* FLASH wait states and prefetching setup.*/
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CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
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CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
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CFLASH0.BIUCR2.R = 0;
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CFLASH0.BIUCR2.R = 0;
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@ -28,42 +28,19 @@
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#if !defined(__DOXYGEN__)
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#if !defined(__DOXYGEN__)
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/* BAM info, SWT off, WTE off, VLE from settings.*/
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/* BAM record.*/
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.section .bam, "ax"
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.section .bam, "ax"
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#if PPC_USE_VLE
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.long 0x015A0000
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.long 0x015A0000
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.long .clear_ecc
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#else
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.long 0x005A0000
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#endif
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.long .init
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.init:
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bl _coreinit
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bl _ivinit
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/* RAM clearing, this device requires a write to all RAM location in
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order to initialize the ECC detection hardware, this is going to
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slow down the startup but there is no way around.*/
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.clear_ecc:
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl cr0, %r4, %r5
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bge cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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b _boot_address
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b _boot_address
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#endif /* !defined(__DOXYGEN__) */
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#endif /* !defined(__DOXYGEN__) */
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@ -0,0 +1,210 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC563Mxx/core.s
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* @brief e200z3 core configuration.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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/**
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* @name BUCSR registers definitions
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* @{
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*/
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#define BUCSR_BPEN 0x00000001
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#define BUCSR_BALLOC_BFI 0x00000200
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/** @} */
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/**
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* @name BUCSR default settings
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* @{
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*/
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#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
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/** @} */
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/**
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* @name MSR register definitions
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* @{
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*/
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#define MSR_UCLE 0x04000000
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#define MSR_SPE 0x02000000
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#define MSR_WE 0x00040000
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#define MSR_CE 0x00020000
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#define MSR_EE 0x00008000
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#define MSR_PR 0x00004000
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#define MSR_FP 0x00002000
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#define MSR_ME 0x00001000
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#define MSR_FE0 0x00000800
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#define MSR_DE 0x00000200
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#define MSR_FE1 0x00000100
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#define MSR_IS 0x00000020
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#define MSR_DS 0x00000010
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#define MSR_RI 0x00000002
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/** @} */
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/**
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* @name MSR default settings
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* @{
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*/
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#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
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/** @} */
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#if !defined(__DOXYGEN__)
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.section .coreinit, "ax"
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.align 2
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.globl _coreinit
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.type _coreinit, @function
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_coreinit:
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* Branch prediction enabled.
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*/
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li %r3, BUCSR_DEFAULT
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mtspr 1013, %r3 /* BUCSR */
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blr
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/*
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* Exception vectors initialization.
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*/
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.global _ivinit
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.type _ivinit, @function
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_ivinit:
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/* MSR initialization.*/
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lis %r3, MSR_DEFAULT@h
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ori %r3, %r3, MSR_DEFAULT@l
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mtMSR %r3
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/* IVPR initialization.*/
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lis %r3, __ivpr_base__@h
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ori %r3, %r3, __ivpr_base__@l
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mtIVPR %r3
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/* IVORs initialization.*/
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lis %r3, _unhandled_exception@h
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ori %r3, %r3, _unhandled_exception@l
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mtspr 400, %r3 /* IVOR0-15 */
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mtspr 401, %r3
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mtspr 402, %r3
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mtspr 403, %r3
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mtspr 404, %r3
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mtspr 405, %r3
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mtspr 406, %r3
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mtspr 407, %r3
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mtspr 408, %r3
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mtspr 409, %r3
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mtspr 410, %r3
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mtspr 411, %r3
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mtspr 412, %r3
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mtspr 413, %r3
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mtspr 414, %r3
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mtspr 415, %r3
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mtspr 528, %r3 /* IVOR32-34 */
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mtspr 529, %r3
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mtspr 530, %r3
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blr
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/*
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* Unhandled exceptions handler.
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*/
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.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
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.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
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.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15, _IVOR32, _IVOR33
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.weak _IVOR34
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.weak _unhandled_exception
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_IVOR0:
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_IVOR1:
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_IVOR2:
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_IVOR3:
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_IVOR5:
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_IVOR6:
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_IVOR7:
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_IVOR8:
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_IVOR9:
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_IVOR11:
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_IVOR12:
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_IVOR13:
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_IVOR14:
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_IVOR15:
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_IVOR32:
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_IVOR33:
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_IVOR34:
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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@ -1,258 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
|
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC563Mxx/ivor.s
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* @brief SPC563Mxx IVORx handlers.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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/*
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* Imports the PPC configuration headers.
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*/
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#define _FROM_ASM_
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#include "chconf.h"
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#include "chcore.h"
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#if !defined(__DOXYGEN__)
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/*
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* INTC registers address.
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*/
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.equ INTC_IACKR, 0xfff48010
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.equ INTC_EOIR, 0xfff48018
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.section .handlers, "ax"
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/*
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* Unhandled exceptions handler.
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*/
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.weak _IVOR0
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_IVOR0:
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.weak _IVOR1
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_IVOR1:
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.weak _IVOR2
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_IVOR2:
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.weak _IVOR3
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_IVOR3:
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.weak _IVOR5
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_IVOR5:
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.weak _IVOR6
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_IVOR6:
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.weak _IVOR7
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_IVOR7:
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.weak _IVOR8
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_IVOR8:
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.weak _IVOR9
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_IVOR9:
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.weak _IVOR11
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_IVOR11:
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.weak _IVOR12
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_IVOR12:
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.weak _IVOR13
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_IVOR13:
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.weak _IVOR14
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_IVOR14:
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.weak _IVOR15
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_IVOR15:
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.weak _unhandled_exception
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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/*
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* _IVOR10 handler (Book-E decrementer).
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*/
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.align 4
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.globl _IVOR10
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.type _IVOR10, @function
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_IVOR10:
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/* Creation of the external stack frame (extctx structure).*/
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stwu %sp, -80(%sp) /* Size of the extctx structure.*/
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#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
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e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
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e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
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e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
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#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
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stw %r0, 32(%sp) /* Saves GPR0. */
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mfSRR0 %r0
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stw %r0, 8(%sp) /* Saves PC. */
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mfSRR1 %r0
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stw %r0, 12(%sp) /* Saves MSR. */
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mfCR %r0
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stw %r0, 16(%sp) /* Saves CR. */
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mfLR %r0
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stw %r0, 20(%sp) /* Saves LR. */
|
|
||||||
mfCTR %r0
|
|
||||||
stw %r0, 24(%sp) /* Saves CTR. */
|
|
||||||
mfXER %r0
|
|
||||||
stw %r0, 28(%sp) /* Saves XER. */
|
|
||||||
stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
|
|
||||||
stw %r4, 40(%sp)
|
|
||||||
stw %r5, 44(%sp)
|
|
||||||
stw %r6, 48(%sp)
|
|
||||||
stw %r7, 52(%sp)
|
|
||||||
stw %r8, 56(%sp)
|
|
||||||
stw %r9, 60(%sp)
|
|
||||||
stw %r10, 64(%sp)
|
|
||||||
stw %r11, 68(%sp)
|
|
||||||
stw %r12, 72(%sp)
|
|
||||||
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
|
|
||||||
/* Reset DIE bit in TSR register.*/
|
|
||||||
lis %r3, 0x0800 /* DIS bit mask. */
|
|
||||||
mtspr 336, %r3 /* TSR register. */
|
|
||||||
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_enter_isr
|
|
||||||
bl dbg_check_lock_from_isr
|
|
||||||
#endif
|
|
||||||
bl chSysTimerHandlerI
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_unlock_from_isr
|
|
||||||
bl dbg_check_leave_isr
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* System tick handler invocation.*/
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_lock
|
|
||||||
#endif
|
|
||||||
bl chSchIsPreemptionRequired
|
|
||||||
cmpli cr0, %r3, 0
|
|
||||||
beq cr0, _ivor_exit
|
|
||||||
bl chSchDoReschedule
|
|
||||||
b _ivor_exit
|
|
||||||
|
|
||||||
/*
|
|
||||||
* _IVOR4 handler (Book-E external interrupt).
|
|
||||||
*/
|
|
||||||
.align 4
|
|
||||||
.globl _IVOR4
|
|
||||||
.type _IVOR4, @function
|
|
||||||
_IVOR4:
|
|
||||||
/* Creation of the external stack frame (extctx structure).*/
|
|
||||||
stwu %sp, -80(%sp) /* Size of the extctx structure.*/
|
|
||||||
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
|
|
||||||
e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
|
|
||||||
e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
|
|
||||||
e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
|
|
||||||
#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
stw %r0, 32(%sp) /* Saves GPR0. */
|
|
||||||
mfSRR0 %r0
|
|
||||||
stw %r0, 8(%sp) /* Saves PC. */
|
|
||||||
mfSRR1 %r0
|
|
||||||
stw %r0, 12(%sp) /* Saves MSR. */
|
|
||||||
mfCR %r0
|
|
||||||
stw %r0, 16(%sp) /* Saves CR. */
|
|
||||||
mfLR %r0
|
|
||||||
stw %r0, 20(%sp) /* Saves LR. */
|
|
||||||
mfCTR %r0
|
|
||||||
stw %r0, 24(%sp) /* Saves CTR. */
|
|
||||||
mfXER %r0
|
|
||||||
stw %r0, 28(%sp) /* Saves XER. */
|
|
||||||
stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
|
|
||||||
stw %r4, 40(%sp)
|
|
||||||
stw %r5, 44(%sp)
|
|
||||||
stw %r6, 48(%sp)
|
|
||||||
stw %r7, 52(%sp)
|
|
||||||
stw %r8, 56(%sp)
|
|
||||||
stw %r9, 60(%sp)
|
|
||||||
stw %r10, 64(%sp)
|
|
||||||
stw %r11, 68(%sp)
|
|
||||||
stw %r12, 72(%sp)
|
|
||||||
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
|
|
||||||
/* Software vector address from the INTC register.*/
|
|
||||||
lis %r3, INTC_IACKR@h
|
|
||||||
ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */
|
|
||||||
lwz %r3, 0(%r3) /* IACKR register value. */
|
|
||||||
lwz %r3, 0(%r3)
|
|
||||||
mtCTR %r3 /* Software handler address. */
|
|
||||||
|
|
||||||
#if PPC_USE_IRQ_PREEMPTION
|
|
||||||
/* Allows preemption while executing the software handler.*/
|
|
||||||
wrteei 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Exectes the software handler.*/
|
|
||||||
bctrl
|
|
||||||
|
|
||||||
#if PPC_USE_IRQ_PREEMPTION
|
|
||||||
/* Prevents preemption again.*/
|
|
||||||
wrteei 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Informs the INTC that the interrupt has been served.*/
|
|
||||||
mbar 0
|
|
||||||
lis %r3, INTC_EOIR@h
|
|
||||||
ori %r3, %r3, INTC_EOIR@l
|
|
||||||
stw %r3, 0(%r3) /* Writing any value should do. */
|
|
||||||
|
|
||||||
/* Verifies if a reschedule is required.*/
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_lock
|
|
||||||
#endif
|
|
||||||
bl chSchIsPreemptionRequired
|
|
||||||
cmpli cr0, %r3, 0
|
|
||||||
beq cr0, _ivor_exit
|
|
||||||
bl chSchDoReschedule
|
|
||||||
|
|
||||||
/* Context restore.*/
|
|
||||||
.globl _ivor_exit
|
|
||||||
_ivor_exit:
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_unlock
|
|
||||||
#endif
|
|
||||||
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
|
|
||||||
e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */
|
|
||||||
e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */
|
|
||||||
e_lmvsrrw 8(%sp) /* Restores PC, MSR. */
|
|
||||||
#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
|
|
||||||
lwz %r4, 40(%sp)
|
|
||||||
lwz %r5, 44(%sp)
|
|
||||||
lwz %r6, 48(%sp)
|
|
||||||
lwz %r7, 52(%sp)
|
|
||||||
lwz %r8, 56(%sp)
|
|
||||||
lwz %r9, 60(%sp)
|
|
||||||
lwz %r10, 64(%sp)
|
|
||||||
lwz %r11, 68(%sp)
|
|
||||||
lwz %r12, 72(%sp)
|
|
||||||
lwz %r0, 8(%sp)
|
|
||||||
mtSRR0 %r0 /* Restores PC. */
|
|
||||||
lwz %r0, 12(%sp)
|
|
||||||
mtSRR1 %r0 /* Restores MSR. */
|
|
||||||
lwz %r0, 16(%sp)
|
|
||||||
mtCR %r0 /* Restores CR. */
|
|
||||||
lwz %r0, 20(%sp)
|
|
||||||
mtLR %r0 /* Restores LR. */
|
|
||||||
lwz %r0, 24(%sp)
|
|
||||||
mtCTR %r0 /* Restores CTR. */
|
|
||||||
lwz %r0, 28(%sp)
|
|
||||||
mtXER %r0 /* Restores XER. */
|
|
||||||
lwz %r0, 32(%sp) /* Restores GPR0. */
|
|
||||||
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
addi %sp, %sp, 80 /* Back to the previous frame. */
|
|
||||||
rfi
|
|
||||||
|
|
||||||
#endif /* !defined(__DOXYGEN__) */
|
|
||||||
|
|
||||||
/** @} */
|
|
||||||
|
|
@ -48,6 +48,7 @@ SECTIONS
|
||||||
{
|
{
|
||||||
__ivpr_base__ = .;
|
__ivpr_base__ = .;
|
||||||
KEEP(*(.bam))
|
KEEP(*(.bam))
|
||||||
|
KEEP(*(.coreinit))
|
||||||
KEEP(*(.crt0))
|
KEEP(*(.crt0))
|
||||||
KEEP(*(.handlers))
|
KEEP(*(.handlers))
|
||||||
. = ALIGN(0x800);
|
. = ALIGN(0x800);
|
||||||
|
|
|
||||||
|
|
@ -2,8 +2,9 @@
|
||||||
PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
|
PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
|
||||||
|
|
||||||
PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/bam.s \
|
PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/bam.s \
|
||||||
|
${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/core.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/vectors.s \
|
${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/vectors.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/ivor.s \
|
${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/crt0.s
|
${CHIBIOS}/os/ports/GCC/PPC/crt0.s
|
||||||
|
|
||||||
PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
|
PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue