diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index 43493d8dd..69c04a41a 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -319,6 +319,11 @@ bool_t sdc_lld_read_blocks(SDCDriver *sdcp, uint8_t *buf, uint32_t n) {
   msg_t msg;
 
   chSysLock();
+  dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4],
+                  n * SDC_BLOCK_SIZE, buf,
+                  (STM32_SDC_SDIO_DMA_PRIORITY << 12) |
+                  DMA_CCR1_MINC | DMA_CCR1_EN);
+
   chDbgAssert(sdcp->thread == NULL, "sdc_lld_read_blocks(), #1", "not NULL");
   sdcp->thread = chThdSelf();
   chSchGoSleepS(THD_STATE_SUSPENDED);
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index e5f4ed6c5..d8ae657a7 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -230,11 +230,11 @@ void spi_lld_start(SPIDriver *spip) {
   /* More DMA setup.*/
   if ((spip->config->cr1 & SPI_CR1_DFF) == 0)
     spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
-                       DMA_CCR1_TEIE;               /* 8 bits transfers.    */
+                    DMA_CCR1_TEIE;                  /* 8 bits transfers.    */
   else
     spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
-                       DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
-                       DMA_CCR1_PSIZE_0;            /* 16 bits transfers.   */
+                    DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
+                    DMA_CCR1_PSIZE_0;               /* 16 bits transfers.   */
 
   /* SPI setup and enable.*/
   spip->spi->CR1  = 0;