From 3ee6ebe343fbdf731ea7d2a214bca62b89a6fd80 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sun, 29 Nov 2020 10:26:02 +0000
Subject: [PATCH] Fixed bug #1137.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13931 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/STM32H7xx/stm32_rcc.h | 28 ++++++++++++++++++++++++
 readme.txt                               |  2 ++
 2 files changed, 30 insertions(+)

diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
index 4f3ad3d2b..75cb81a74 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
@@ -489,6 +489,34 @@
 #define rccResetADC3() rccResetAHB4(RCC_AHB4RSTR_ADC3RST)
 /** @} */
 
+/**
+ * @name    CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the CRC peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB4(RCC_AHB4ENR_CRCEN, lp)
+
+/**
+ * @brief   Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB4(RCC_AHB4ENR_CRCEN)
+
+/**
+ * @brief   Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB4(RCC_AHB4RSTR_CRCRST)
+/** @} */
+
 /**
  * @name    CRYP peripheral specific RCC operations
  * @{
diff --git a/readme.txt b/readme.txt
index 9cfe23f6b..8cc120611 100644
--- a/readme.txt
+++ b/readme.txt
@@ -123,6 +123,8 @@
        MEMS Accelerometers.
 - NEW: Safer messages mechanism for sandboxes (to be backported to 20.3.1).
 - NEW: Added latency measurement test application.
+- FIX: Fixed STM32H7xx Missing CRC RCC macros (bug #1137)
+       (backported to 20.3.3).
 - FIX: Fixed STM32L0x wrong ISR names for USART 4 and 5 (bug #1136)
        (backported to 20.3.3).
 - FIX: Fixed OTG_FS error on STM32H7 (bug #1135)