Fixed bug 3484942.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@3935 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT
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# This could be handy for archiving the generated documentation or
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# if some version control system is used.
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PROJECT_NUMBER = 2.4.0
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PROJECT_NUMBER = 2.4.1
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# Using the PROJECT_BRIEF tag one can provide an optional one line description
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# for a project that appears at the top of each page and should give viewer
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@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT
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# This could be handy for archiving the generated documentation or
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# if some version control system is used.
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PROJECT_NUMBER = 2.4.0
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PROJECT_NUMBER = 2.4.1
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# Using the PROJECT_BRIEF tag one can provide an optional one line description
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# for a project that appears at the top of each page and should give viewer
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@ -13,7 +13,7 @@
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<tbody>
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<tr style="height: 56px;">
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<td style="padding-left: 0.5em;">
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<div id="projectname">ChibiOS/RT <span id="projectnumber">2.4.0</span></div>
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<div id="projectname">ChibiOS/RT <span id="projectnumber">2.4.1</span></div>
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</td>
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</tr>
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</tbody>
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@ -20,7 +20,7 @@ $(document).ready(initResizable);
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<tbody>
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<tr style="height: 92px;">
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<td style="padding-left: 0.5em;">
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<div id="projectname">ChibiOS/RT<br><span id="projectnumber">2.4.0</span></div>
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<div id="projectname">ChibiOS/RT<br><span id="projectnumber">2.4.1</span></div>
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</td>
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<td style="padding-left: 3em;">
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<script type="text/javascript"><!--
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@ -53,11 +53,8 @@
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/**
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* @brief Maximum HSE clock frequency.
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* @note This value is arbitrary defined, the current datasheet does not
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* define a maximum value (it is TBD). A value of 36MHz is mentioned
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* but without relationship to VDD ranges.
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*/
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#define STM32_ADCCLK_MAX 42000000
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#define STM32_ADCCLK_MAX 30000000
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/** @} */
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/**
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@ -130,9 +127,9 @@
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/**
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* @brief ADC common clock divider.
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* @note This setting is influenced by the VDDA voltage and other
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* external conditions, please refer to the STM32L15x datasheet
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* external conditions, please refer to the STM32F2xx datasheet
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* for more info.<br>
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* See section 6.3.15 "12-bit ADC characteristics".
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* See section 5.3.20 "12-bit ADC characteristics".
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*/
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#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
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@ -26,8 +26,8 @@
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*/
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/**
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* @file STM32F4xx/hal_lld.c
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* @brief STM32F4xx HAL subsystem low level driver source.
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* @file STM32F2xx/hal_lld.c
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* @brief STM32F2xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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@ -53,11 +53,8 @@
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/**
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* @brief Maximum HSE clock frequency.
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* @note This value is arbitrary defined, the current datasheet does not
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* define a maximum value (it is TBD). A value of 36MHz is mentioned
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* but without relationship to VDD ranges.
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*/
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#define STM32_ADCCLK_MAX 42000000
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#define STM32_ADCCLK_MAX 36000000
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/** @} */
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/**
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@ -130,9 +127,9 @@
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/**
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* @brief ADC common clock divider.
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* @note This setting is influenced by the VDDA voltage and other
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* external conditions, please refer to the STM32L15x datasheet
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* external conditions, please refer to the STM32F4xx datasheet
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* for more info.<br>
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* See section 6.3.15 "12-bit ADC characteristics".
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* See section 5.3.20 "12-bit ADC characteristics".
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*/
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#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
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@ -47,7 +47,7 @@
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/**
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* @brief Kernel version string.
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*/
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#define CH_KERNEL_VERSION "2.4.0"
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#define CH_KERNEL_VERSION "2.4.1"
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/**
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* @name Kernel version
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@ -66,7 +66,7 @@
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/**
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* @brief Kernel version patch number.
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*/
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#define CH_KERNEL_PATCH 0
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#define CH_KERNEL_PATCH 1
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/** @} */
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/*
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@ -78,6 +78,10 @@
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*** Releases ***
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*****************************************************************************
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*** 2.4.1 ***
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- FIX: Fixed various minor documentation errors and fixed ADC maximum
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frequency limit in STM32F2/F4 ADC drivers (bug 3484942).
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*** 2.4.0 ***
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- NEW: Implemented new makefile system for ARM GCC ports, now objects,
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listings and output files are generated into a "build" directory and not
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