Added MSI PLL support to L4.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8483 35acf78f-673a-0410-8e92-d51de3d6d3f4

demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h

@@ -43,7 +43,8 @@
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_LSI_ENABLED                   TRUE
 #define STM32_HSE_ENABLED                   FALSE
-#define STM32_LSE_ENABLED                   FALSE
+#define STM32_LSE_ENABLED                   TRUE
+#define STM32_MSIPLL_ENABLED                TRUE
 #define STM32_ADC_CLOCK_ENABLED             TRUE
 #define STM32_USB_CLOCK_ENABLED             TRUE
 #define STM32_SAI1_CLOCK_ENABLED            TRUE

os/hal/boards/ST_NUCLEO_L476RG/board.h

@@ -29,13 +29,14 @@
 
 /*
  * Board oscillators-related settings.
- * NOTE: LSE not fitted.
  * NOTE: HSE not fitted.
  */
 #if !defined(STM32_LSECLK)
-#define STM32_LSECLK                0U
+#define STM32_LSECLK                32768U
 #endif
 
+#define STM32_LSEDRV                (3U << 3U)
+
 #if !defined(STM32_HSECLK)
 #define STM32_HSECLK                0U
 #endif

os/hal/boards/ST_NUCLEO_L476RG/cfg/board.chcfg

@@ -15,7 +15,7 @@
   <clocks
     HSEFrequency="0"
     HSEBypass="false"
-    LSEFrequency="0"
+    LSEFrequency="32768"
     LSEBypass="false"
     LSEDrive="3 High Drive (default)"
     VDD="300" />

os/hal/ports/STM32/STM32L4xx/hal_lld.c

@@ -53,9 +53,6 @@ uint32_t SystemCoreClock = STM32_HCLK;
  */
 static void hal_lld_backup_domain_init(void) {
 
-  /* Backup domain access enabled and left open.*/
-  PWR->CR1 |= PWR_CR1_DBP;
-
   /* Reset BKP domain if different clock source selected.*/
   if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
     /* Backup domain reset.*/
@@ -63,19 +60,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR = 0;
   }
 
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Wait until LSE is stable.    */
-#endif
-
 #if HAL_USE_RTC
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
@@ -184,12 +168,33 @@ void stm32_clock_init(void) {
     ;                                       /* Wait until LSI is stable.    */
 #endif
 
+  /* Backup domain access enabled and left open.*/
+  PWR->CR1 |= PWR_CR1_DBP;
+
+#if STM32_LSE_ENABLED
+  /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                       /* Wait until LSE is stable.    */
+#endif
+
+#if STM32_MSIPLL_ENABLED
+  /* MSI PLL activation.*/
+  RCC->CR |= RCC_CR_MSIPLLEN;
+#endif
+
 #if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
   /* PLLM and PLLSRC are common to all PLLs.*/
-  RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
-                 STM32_PLLQ | STM32_PLLQEN |
-                 STM32_PLLP | STM32_PLLPEN |
-                 STM32_PLLN | STM32_PLLM   |
+  RCC->PLLCFGR = STM32_PLLR   | STM32_PLLREN |
+                 STM32_PLLQ   | STM32_PLLQEN |
+                 STM32_PLLP   | STM32_PLLPEN |
+                 STM32_PLLN   | STM32_PLLM   |
                  STM32_PLLSRC;
 #endif
 

os/hal/ports/STM32/STM32L4xx/hal_lld.h

@@ -381,6 +381,13 @@
 #define STM32_LSE_ENABLED                   FALSE
 #endif
 
+/**
+ * @brief   Enables or disables the MSI PLL on LSE clock source.
+ */
+#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__)
+#define STM32_MSIPLL_ENABLED                FALSE
+#endif
+
 /**
  * @brief   ADC clock setting.
  */
@@ -733,6 +740,21 @@
 #error "Using a wrong mcuconf.h file, STM32L4xx_MCUCONF not defined"
 #endif
 
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
 /* Voltage related limits.*/
 #if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
 /**
@@ -1067,6 +1089,10 @@
     #error "LSE not enabled, required by STM32_LSCOSEL"
   #endif
 
+  #if STM32_MSIPLL_ENABLED == TRUE
+    #error "LSE not enabled, required by STM32_MSIPLL_ENABLED"
+  #endif
+
 #endif /* !STM32_LSE_ENABLED */
 
 /**