Moved cache initialization into startup files.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8220 35acf78f-673a-0410-8e92-d51de3d6d3f4

demos/STM32/RT-STM32F746G-DISCOVERY/main.c

@@ -40,11 +40,6 @@ static THD_FUNCTION(Thread1, arg) {
  */
 int main(void) {
 
-  SCB_InvalidateICache();
-  SCB_EnableICache();
-  SCB_CleanInvalidateDCache();
-  SCB_EnableDCache();
-
   /*
    * System initializations.
    * - HAL initialization, this also initializes the configured device drivers

os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s

@@ -56,6 +56,13 @@
                                              CONTROL_MODE_PRIVILEGED)
 #endif
 
+/**
+ * @brief   Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE                      TRUE
+#endif
+
 /**
  * @brief   Stack segments initialization switch.
  */
@@ -129,6 +136,11 @@ Reset_Handler:
                 msr     CONTROL, r0
                 isb
 
+#if CRT0_INIT_CORE == TRUE
+                /* Core initialization.*/
+                bl      __core_init
+#endif
+
                 /* Early initialization..*/
                 bl      __early_init
 

os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s

@@ -54,6 +54,17 @@
 /* Module pre-compile time settings.                                         */
 /*===========================================================================*/
 
+/**
+ * @brief   FPU initialization switch.
+ */
+#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
+#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
+#define CRT0_INIT_FPU                       CORTEX_USE_FPU
+#else
+#define CRT0_INIT_FPU                       FALSE
+#endif
+#endif
+
 /**
  * @brief   Control special register initialization value.
  * @details The system is setup to run in privileged mode using the PSP
@@ -64,6 +75,13 @@
                                              CONTROL_MODE_PRIVILEGED)
 #endif
 
+/**
+ * @brief   Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE                      TRUE
+#endif
+
 /**
  * @brief   Stack segments initialization switch.
  */
@@ -106,17 +124,6 @@
 #define CRT0_CALL_DESTRUCTORS               TRUE
 #endif
 
-/**
- * @brief   FPU initialization switch.
- */
-#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
-#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
-#define CRT0_INIT_FPU                       CORTEX_USE_FPU
-#else
-#define CRT0_INIT_FPU                       FALSE
-#endif
-#endif
-
 /**
  * @brief   FPU FPCCR register initialization value.
  * @note    Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
@@ -199,7 +206,12 @@ Reset_Handler:
                 msr     CONTROL, r0
                 isb
 
-                /* Early initialization..*/
+#if CRT0_INIT_CORE == TRUE
+                /* Core initialization.*/
+                bl      __core_init
+#endif
+
+                /* Early initialization.*/
                 bl      __early_init
 
 #if CRT0_INIT_STACKS == TRUE

os/common/ports/ARMCMx/compilers/GCC/crt1.c

@@ -27,11 +27,31 @@
 
 #include <stdbool.h>
 
+#include "cmparams.h"
+
+/**
+ * @brief   Architecture-dependent core initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ *          and before the DATA and BSS segments initialization.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __core_init(void) {
+
+#if __CORTEX_M == 7
+  SCB_EnableICache();
+  SCB_EnableDCache();
+#endif
+}
+
 /**
  * @brief   Early initialization.
- * @details This hook is invoked immediately after the stack initialization
- *          and before the DATA and BSS segments initialization. The
- *          default behavior is to do nothing.
+ * @details This hook is invoked immediately after the stack and core
+ *          initialization and before the DATA and BSS segments
+ *          initialization.
  * @note    This function is a weak symbol.
  */
 #if !defined(__DOXYGEN__)

os/hal/ports/STM32/STM32F7xx/hal_lld.c

@@ -146,6 +146,10 @@ void hal_lld_init(void) {
                      MPU_RASR_SIZE_512K |
                      MPU_RASR_ENABLE);
   mpuEnable(MPU_CTRL_PRIVDEFENA);
+
+  /* Invalidating data cache to make sure that the MPU settings are taken
+     immediately.*/
+  SCB_InvalidateDCache();
 #endif
 #endif
 

testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c

@@ -123,11 +123,6 @@ int main(void) {
   halInit();
   chSysInit();
 
-  SCB_InvalidateICache();
-  SCB_EnableICache();
-  SCB_InvalidateDCache();
-  SCB_EnableDCache();
-
   /*
    * Activates the serial driver 1 using the driver default configuration.
    */