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Added BDMA support to the STM32H7xx port. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11232 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2018-01-07 19:22:53 +00:00
parent 5a733a0d43
commit 4148fb3cb7
14 changed files with 1329 additions and 255 deletions
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2
os/hal/ports/STM32/LLD/BDMAv1/driver.mk Normal file
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c
PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1

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os/hal/ports/STM32/LLD/BDMAv1/notes.txt Normal file
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STM32 BDMAv1 driver.
Driver capability:
- The driver supports the "basic" DMA controller.
The file registry must export:
STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro
is not exported then the ISR is not declared.
STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7).
STM32_DMA_CACHE_HANDLING - TRUE if the device requires explicit cache
handling on DMA buffers.

381
os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file BDMAv1/stm32_bdma.c
* @brief BDMA helper driver code.
*
* @addtogroup STM32_BDMA
* @details BDMA sharing helper driver. In the STM32 the BDMA streams are a
* shared resource, this driver allows to allocate and free BDMA
* streams at runtime in order to allow all the other device
* drivers to coordinate the access to the resource.
* @note The BDMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
* ISRs when allocating streams.
* @{
*/
#include "hal.h"
/* The following macro is only defined if some driver requiring BDMA services
has been enabled.*/
#if defined(STM32_BDMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief Mask of the BDMA streams in @p bdma_streams_mask.
*/
#define STM32_BDMA_STREAMS_MASK 0x000000FFU
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief BDMA streams descriptors.
* @details This table keeps the association between an unique stream
* identifier and the involved physical registers.
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_BDMA1_STREAM1, @p STM32_BDMA1_STREAM2 etc.
*/
const stm32_bdma_stream_t _stm32_bdma_streams[STM32_BDMA_STREAMS] = {
{BDMA, BDMA_Channel0, 0, DMAMUX2_Channel0, 0, STM32_BDMA1_CH0_NUMBER},
{BDMA, BDMA_Channel1, 4, DMAMUX2_Channel1, 1, STM32_BDMA1_CH1_NUMBER},
{BDMA, BDMA_Channel2, 8, DMAMUX2_Channel2, 2, STM32_BDMA1_CH2_NUMBER},
{BDMA, BDMA_Channel3, 12, DMAMUX2_Channel3, 3, STM32_BDMA1_CH3_NUMBER},
{BDMA, BDMA_Channel4, 16, DMAMUX2_Channel4, 4, STM32_BDMA1_CH4_NUMBER},
{BDMA, BDMA_Channel5, 20, DMAMUX2_Channel5, 5, STM32_BDMA1_CH5_NUMBER},
{BDMA, BDMA_Channel6, 24, DMAMUX2_Channel6, 6, STM32_BDMA1_CH6_NUMBER},
{BDMA, BDMA_Channel7, 28, DMAMUX2_Channel7, 7, STM32_BDMA1_CH7_NUMBER}
};
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief BDMA ISR redirector type.
*/
typedef struct {
stm32_bdmaisr_t func; /**< @brief BDMA callback function. */
void *param; /**< @brief BDMA callback parameter.*/
} bdma_isr_redir_t;
/**
* @brief BDMA driver base structure.
*/
static struct {
/**
* @brief Mask of the allocated streams.
*/
uint32_t streams_mask;
/**
* @brief BDMA IRQ redirectors.
*/
bdma_isr_redir_t isr_redir[STM32_BDMA_STREAMS];
} bdma;
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief BDMA1 stream 0 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH0_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 0U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 0U;
if (bdma.isr_redir[0].func)
bdma.isr_redir[0].func(bdma.isr_redir[0].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 1 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH1_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 4U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 4U;
if (bdma.isr_redir[1].func)
bdma.isr_redir[1].func(bdma.isr_redir[1].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 2 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH2_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 8U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 8U;
if (bdma.isr_redir[2].func)
bdma.isr_redir[2].func(bdma.isr_redir[2].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 3 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH3_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 12U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 12U;
if (bdma.isr_redir[3].func)
bdma.isr_redir[3].func(bdma.isr_redir[3].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 4 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH4_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 16U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 16U;
if (bdma.isr_redir[4].func)
bdma.isr_redir[4].func(bdma.isr_redir[4].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 5 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH5_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 20U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 20U;
if (bdma.isr_redir[5].func)
bdma.isr_redir[5].func(bdma.isr_redir[5].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 6 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH6_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 24U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 24U;
if (bdma.isr_redir[6].func)
bdma.isr_redir[6].func(bdma.isr_redir[6].param, flags);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief BDMA1 stream 7 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_BDMA1_CH7_HANDLER) {
uint32_t flags;
OSAL_IRQ_PROLOGUE();
flags = (BDMA->ISR >> 28U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 28U;
if (bdma.isr_redir[7].func)
bdma.isr_redir[7].func(bdma.isr_redir[7].param, flags);
OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief STM32 BDMA helper initialization.
*
* @init
*/
void bdmaInit(void) {
unsigned i;
bdma.streams_mask = 0U;
for (i = 0; i < STM32_BDMA_STREAMS; i++) {
_stm32_bdma_streams[i].channel->CCR = 0U;
bdma.isr_redir[i].func = NULL;
bdma.isr_redir[i].param = NULL;
}
BDMA->IFCR = 0xFFFFFFFFU;
}
/**
* @brief Allocates a BDMA stream.
* @details The stream is allocated and, if required, the BDMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p bdmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] priority IRQ priority for the BDMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval false no error, stream taken.
* @retval true error, stream already taken.
*
* @special
*/
bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
uint32_t priority,
stm32_bdmaisr_t func,
void *param) {
osalDbgCheck(stp != NULL);
/* Checks if the stream is already taken.*/
if ((bdma.streams_mask & (1U << stp->selfindex)) != 0U)
return true;
/* Installs the BDMA handler.*/
bdma.isr_redir[stp->selfindex].func = func;
bdma.isr_redir[stp->selfindex].param = param;
bdma.streams_mask |= (1U << stp->selfindex);
/* Enabling BDMA clocks required by the current streams set.*/
if ((bdma.streams_mask & STM32_BDMA_STREAMS_MASK) == 0U) {
rccEnableBDMA1(false);
}
/* Putting the stream in a safe state.*/
bdmaStreamDisable(stp);
stp->channel->CCR = STM32_BDMA_CR_RESET_VALUE;
/* Enables the associated IRQ vector if not already enabled and if a
callback is defined.*/
if (func != NULL) {
nvicEnableVector(stp->vector, priority);
}
return false;
}
/**
* @brief Associates a peripheral request to a BDMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] stp pointer to a @p stm32_bdma_stream_t structure
* @param[in] per peripheral identifier
*
* @special
*/
void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per) {
osalDbgCheck(per < 256U);
stp->mux->CCR = per;
}
/**
* @brief Releases a BDMA stream.
* @details The stream is freed and, if required, the BDMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @special
*/
void bdmaStreamRelease(const stm32_bdma_stream_t *stp) {
osalDbgCheck(stp != NULL);
/* Check if the streams is not taken.*/
osalDbgAssert((bdma.streams_mask & (1U << stp->selfindex)) != 0U,
"not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(stp->vector);
/* Marks the stream as not allocated.*/
bdma.streams_mask &= ~(1U << stp->selfindex);
/* Clearing associated handler and parameter.*/
bdma.isr_redir->func = NULL;
bdma.isr_redir->param = NULL;
/* Shutting down clocks that are no more required, if any.*/
if ((bdma.streams_mask & STM32_BDMA_STREAMS_MASK) == 0U) {
rccDisableBDMA1();
}
}
#endif /* STM32_BDMA_REQUIRED */
/** @} */

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os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file BDMAv1/stm32_bdma.h
* @brief BDMA helper driver header.
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "BDMA channels" are referred as "BDMA streams".
*
* @addtogroup STM32_BDMA
* @{
*/
#ifndef STM32_BDMA_H
#define STM32_BDMA_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Total number of BDMA streams.
* @details This is the total number of streams among all the BDMA units.
*/
#define STM32_BDMA_STREAMS 8U
/**
* @brief Mask of the ISR bits passed to the BDMA callback functions.
*/
#define STM32_BDMA_ISR_MASK 0x0EU
/**
* @brief Checks if a BDMA priority is within the valid range.
*
* @param[in] prio BDMA priority
* @retval The check result.
* @retval false invalid BDMA priority.
* @retval true correct BDMA priority.
*/
#define STM32_BDMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Checks if a BDMA channel is within the valid range.
*
* @param[in] ch BDMA channel
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
*/
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) <= 15U))
/**
* @name BDMA streams identifiers
* @{
*/
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_bdma_stream_t constant structure
* associated to the BDMA stream.
*/
#define STM32_BDMA_STREAM(id) (&_stm32_bdma_streams[id])
#define STM32_BDMA1_STREAM0 STM32_BDMA_STREAM(0)
#define STM32_BDMA1_STREAM1 STM32_BDMA_STREAM(1)
#define STM32_BDMA1_STREAM2 STM32_BDMA_STREAM(2)
#define STM32_BDMA1_STREAM3 STM32_BDMA_STREAM(3)
#define STM32_BDMA1_STREAM4 STM32_BDMA_STREAM(4)
#define STM32_BDMA1_STREAM5 STM32_BDMA_STREAM(5)
#define STM32_BDMA1_STREAM6 STM32_BDMA_STREAM(6)
#define STM32_BDMA1_STREAM7 STM32_BDMA_STREAM(7)
/** @} */
/**
* @name CR register constants
* @{
*/
#define STM32_BDMA_CR_RESET_VALUE 0x00000000U
#define STM32_BDMA_CR_EN BDMA_CCR_EN_Msk
#define STM32_BDMA_CR_TCIE BDMA_CCR_TCIE
#define STM32_BDMA_CR_HTIE BDMA_CCR_HTIE
#define STM32_BDMA_CR_TEIE BDMA_CCR_TEIE
#define STM32_BDMA_CR_DIR_MASK (BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)
#define STM32_BDMA_CR_DIR_P2M 0U
#define STM32_BDMA_CR_DIR_M2P BDMA_CCR_DIR
#define STM32_BDMA_CR_DIR_M2M BDMA_CCR_MEM2MEM
#define STM32_BDMA_CR_CIRC BDMA_CCR_CIRC
#define STM32_BDMA_CR_PINC BDMA_CCR_PINC
#define STM32_BDMA_CR_MINC BDMA_CCR_MINC
#define STM32_BDMA_CR_PSIZE_MASK BDMA_CCR_PSIZE_Msk
#define STM32_BDMA_CR_PSIZE_BYTE 0U
#define STM32_BDMA_CR_PSIZE_HWORD BDMA_CCR_PSIZE_0
#define STM32_BDMA_CR_PSIZE_WORD BDMA_CCR_PSIZE_1
#define STM32_BDMA_CR_MSIZE_MASK BDMA_CCR_MSIZE_Msk
#define STM32_BDMA_CR_MSIZE_BYTE 0U
#define STM32_BDMA_CR_MSIZE_HWORD BDMA_CCR_MSIZE_0
#define STM32_BDMA_CR_MSIZE_WORD BDMA_CCR_MSIZE_1
#define STM32_BDMA_CR_SIZE_MASK (STM32_BDMA_CR_PSIZE_MASK | \
STM32_BDMA_CR_MSIZE_MASK)
#define STM32_BDMA_CR_PL_MASK BDMA_CCR_PL_Msk
#define STM32_BDMA_CR_PL(n) ((n) << 12U)
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_BDMA_ISR_TEIF BDMA_ISR_TEIF1
#define STM32_BDMA_ISR_HTIF BDMA_ISR_HTIF1
#define STM32_BDMA_ISR_TCIF BDMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
#if !defined(STM32_HAS_BDMA1)
#error "STM32_HAS_BDMA1 missing in registry"
#endif
#if !defined(STM32_BDMA1_CH0_HANDLER)
#error "STM32_BDMA1_CH0_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH1_HANDLER)
#error "STM32_BDMA1_CH1_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH2_HANDLER)
#error "STM32_BDMA1_CH2_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH3_HANDLER)
#error "STM32_BDMA1_CH3_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH4_HANDLER)
#error "STM32_BDMA1_CH4_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH5_HANDLER)
#error "STM32_BDMA1_CH5_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH6_HANDLER)
#error "STM32_BDMA1_CH6_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH7_HANDLER)
#error "STM32_BDMA1_CH7_HANDLER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH0_NUMBER)
#error "STM32_BDMA1_CH0_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH1_NUMBER)
#error "STM32_BDMA1_CH1_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH2_NUMBER)
#error "STM32_BDMA1_CH2_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH3_NUMBER)
#error "STM32_BDMA1_CH3_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH4_NUMBER)
#error "STM32_BDMA1_CH4_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH5_NUMBER)
#error "STM32_BDMA1_CH5_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH6_NUMBER)
#error "STM32_BDMA1_CH6_NUMBER missing in registry"
#endif
#if !defined(STM32_BDMA1_CH7_NUMBER)
#error "STM32_BDMA1_CH7_NUMBER missing in registry"
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 BDMA stream descriptor structure.
*/
typedef struct {
BDMA_TypeDef *bdma ; /**< @brief Associated BDMA. */
BDMA_Channel_TypeDef *channel; /**< @brief Associated BDMA channel.*/
uint8_t ishift; /**< @brief Bit offset in ISR and
IFCR registers. */
DMAMUX_Channel_TypeDef *mux; /**< @brief Associated BDMA stream. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_bdma_stream_t;
/**
* @brief STM32 BDMA ISR function type.
*
* @param[in] p parameter for the registered function
* @param[in] flags pre-shifted content of the ISR register, the bits
* are aligned to bit zero
*/
typedef void (*stm32_bdmaisr_t)(void *p, uint32_t flags);
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a BDMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] addr value to be written in the CPAR register
*
* @special
*/
#define bdmaStreamSetPeripheral(stp, addr) { \
(stp)->channel->CPAR = (uint32_t)(addr); \
}
/**
* @brief Associates a memory destination to a BDMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] addr value to be written in the CMAR register
*
* @special
*/
#define bdmaStreamSetMemory(stp, addr) { \
(stp)->channel->CMAR = (uint32_t)(addr); \
}
/**
* @brief Sets the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define bdmaStreamSetTransactionSize(stp, size) { \
(stp)->channel->CNDTR = (uint32_t)(size); \
}
/**
* @brief Returns the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @return The number of transfers to be performed.
*
* @special
*/
#define bdmaStreamGetTransactionSize(stp) ((size_t)((stp)->channel->CNDTR))
/**
* @brief Programs the stream mode settings.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] mode value to be written in the CCR register
*
* @special
*/
#define bdmaStreamSetMode(stp, mode) { \
(stp)->channel->CCR = (uint32_t)(mode); \
}
/**
* @brief BDMA stream enable.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @special
*/
#define bdmaStreamEnable(stp) { \
(stp)->channel->CCR |= STM32_BDMA_CR_EN; \
}
/**
* @brief BDMA stream disable.
* @details The function disables the specified stream and then clears any
* pending interrupt.
* @note This function can be invoked in both ISR or thread context.
* @note Interrupts enabling flags are set to zero after this call, see
* bug 3607518.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @special
*/
#define bdmaStreamDisable(stp) { \
(stp)->channel->CCR &= ~(STM32_BDMA_CR_TCIE | STM32_BDMA_CR_HTIE | \
STM32_BDMA_CR_TEIE | STM32_BDMA_CR_EN); \
bdmaStreamClearInterrupt(stp); \
}
/**
* @brief BDMA stream interrupt sources clear.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @special
*/
#define bdmaStreamClearInterrupt(stp) { \
(stp)->bdma->IFCR = STM32_BDMA_ISR_MASK << (stp)->ishift; \
}
/**
* @brief Starts a memory to memory operation using the specified stream.
* @note The default transfer data mode is "byte to byte" but it can be
* changed by specifying extra options in the @p mode parameter.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_BDMA_CR_MINC
* - @p STM32_BDMA_CR_PINC
* - @p STM32_BDMA_CR_DIR_M2M
* - @p STM32_BDMA_CR_EN
* .
* @param[in] src source address
* @param[in] dst destination address
* @param[in] n number of data units to copy
*/
#define bdmaStartMemCopy(stp, mode, src, dst, n) { \
bdmaStreamSetPeripheral(stp, src); \
bdmaStreamSetMemory0(stp, dst); \
bdmaStreamSetTransactionSize(stp, n); \
bdmaStreamSetMode(stp, (mode) | \
STM32_BDMA_CR_MINC | STM32_BDMA_CR_PINC | \
STM32_BDMA_CR_DIR_M2M | STM32_BDMA_CR_EN); \
}
/**
* @brief Polled wait for BDMA transfer end.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post After use the stream can be released using @p bdmaStreamRelease().
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*/
#define bdmaWaitCompletion(stp) { \
while ((stp)->channel->CNDTR > 0U) \
; \
bdmaStreamDisable(stp); \
}
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_bdma_stream_t _stm32_bdma_streams[STM32_BDMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void bdmaInit(void);
bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
uint32_t priority,
stm32_bdmaisr_t func,
void *param);
void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per);
void bdmaStreamRelease(const stm32_bdma_stream_t *stp);
#ifdef __cplusplus
}
#endif
#endif /* STM32_BDMA_H */
/** @} */

170
os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c
View File

@ -40,12 +40,12 @@
/*===========================================================================*/
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
* @brief Mask of the DMA1 streams in @p dma.streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x000000FFU
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
* @brief Mask of the DMA2 streams in @p dma.streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x0000FF00U
@ -61,22 +61,22 @@
* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
{DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
{DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
{DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
{DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
{DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
{DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
{DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
{DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
{DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
{DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
{DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
{DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
{DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
{DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
{DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
{DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
{DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
{DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
{DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
{DMA2_Stream2, &DMA2->LIFCR, 16, DMAMUX1_Channel10, 10, STM32_DMA2_CH2_NUMBER},
{DMA2_Stream3, &DMA2->LIFCR, 22, DMAMUX1_Channel11, 11, STM32_DMA2_CH3_NUMBER},
{DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
{DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
{DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Stream6, &DMA2->HIFCR, 16, DMAMUX1_Channel14, 14, STM32_DMA2_CH6_NUMBER},
{DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER},
{DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER}
};
/*===========================================================================*/
@ -92,14 +92,18 @@ typedef struct {
} dma_isr_redir_t;
/**
* @brief Mask of the allocated streams.
* @brief DMA driver base structure.
*/
static uint32_t dma_streams_mask;
/**
* @brief DMA IRQ redirectors.
*/
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
static struct {
/**
* @brief Mask of the allocated streams.
*/
uint32_t streams_mask;
/**
* @brief DMA IRQ redirectors.
*/
dma_isr_redir_t isr_redir[STM32_DMA_STREAMS];
} dma;
/*===========================================================================*/
/* Driver local functions. */
@ -121,8 +125,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) {
flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 0U;
if (dma_isr_redir[0].func)
dma_isr_redir[0].func(dma_isr_redir[0].param, flags);
if (dma.isr_redir[0].func)
dma.isr_redir[0].func(dma.isr_redir[0].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -139,8 +143,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 6U;
if (dma_isr_redir[1].func)
dma_isr_redir[1].func(dma_isr_redir[1].param, flags);
if (dma.isr_redir[1].func)
dma.isr_redir[1].func(dma.isr_redir[1].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -157,8 +161,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 16U;
if (dma_isr_redir[2].func)
dma_isr_redir[2].func(dma_isr_redir[2].param, flags);
if (dma.isr_redir[2].func)
dma.isr_redir[2].func(dma.isr_redir[2].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -175,8 +179,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 22U;
if (dma_isr_redir[3].func)
dma_isr_redir[3].func(dma_isr_redir[3].param, flags);
if (dma.isr_redir[3].func)
dma.isr_redir[3].func(dma.isr_redir[3].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -193,8 +197,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 0U;
if (dma_isr_redir[4].func)
dma_isr_redir[4].func(dma_isr_redir[4].param, flags);
if (dma.isr_redir[4].func)
dma.isr_redir[4].func(dma.isr_redir[4].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -211,8 +215,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 6U;
if (dma_isr_redir[5].func)
dma_isr_redir[5].func(dma_isr_redir[5].param, flags);
if (dma.isr_redir[5].func)
dma.isr_redir[5].func(dma.isr_redir[5].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -229,8 +233,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 16U;
if (dma_isr_redir[6].func)
dma_isr_redir[6].func(dma_isr_redir[6].param, flags);
if (dma.isr_redir[6].func)
dma.isr_redir[6].func(dma.isr_redir[6].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -247,8 +251,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 22U;
if (dma_isr_redir[7].func)
dma_isr_redir[7].func(dma_isr_redir[7].param, flags);
if (dma.isr_redir[7].func)
dma.isr_redir[7].func(dma.isr_redir[7].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -265,8 +269,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) {
flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 0U;
if (dma_isr_redir[8].func)
dma_isr_redir[8].func(dma_isr_redir[8].param, flags);
if (dma.isr_redir[8].func)
dma.isr_redir[8].func(dma.isr_redir[8].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -283,8 +287,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 6U;
if (dma_isr_redir[9].func)
dma_isr_redir[9].func(dma_isr_redir[9].param, flags);
if (dma.isr_redir[9].func)
dma.isr_redir[9].func(dma.isr_redir[9].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -301,8 +305,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 16U;
if (dma_isr_redir[10].func)
dma_isr_redir[10].func(dma_isr_redir[10].param, flags);
if (dma.isr_redir[10].func)
dma.isr_redir[10].func(dma.isr_redir[10].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -319,8 +323,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 22U;
if (dma_isr_redir[11].func)
dma_isr_redir[11].func(dma_isr_redir[11].param, flags);
if (dma.isr_redir[11].func)
dma.isr_redir[11].func(dma.isr_redir[11].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -337,8 +341,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 0U;
if (dma_isr_redir[12].func)
dma_isr_redir[12].func(dma_isr_redir[12].param, flags);
if (dma.isr_redir[12].func)
dma.isr_redir[12].func(dma.isr_redir[12].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -355,8 +359,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 6U;
if (dma_isr_redir[13].func)
dma_isr_redir[13].func(dma_isr_redir[13].param, flags);
if (dma.isr_redir[13].func)
dma.isr_redir[13].func(dma.isr_redir[13].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -373,8 +377,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 16U;
if (dma_isr_redir[14].func)
dma_isr_redir[14].func(dma_isr_redir[14].param, flags);
if (dma.isr_redir[14].func)
dma.isr_redir[14].func(dma.isr_redir[14].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -391,8 +395,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 22U;
if (dma_isr_redir[15].func)
dma_isr_redir[15].func(dma_isr_redir[15].param, flags);
if (dma.isr_redir[15].func)
dma.isr_redir[15].func(dma.isr_redir[15].param, flags);
OSAL_IRQ_EPILOGUE();
}
@ -409,10 +413,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
void dmaInit(void) {
unsigned i;
dma_streams_mask = 0U;
dma.streams_mask = 0U;
for (i = 0U; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].stream->CR = 0U;
dma_isr_redir[i].func = NULL;
dma.isr_redir[i].func = NULL;
dma.isr_redir[i].param = NULL;
}
DMA1->LIFCR = 0xFFFFFFFFU;
DMA1->HIFCR = 0xFFFFFFFFU;
@ -434,7 +439,7 @@ void dmaInit(void) {
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
@ -444,58 +449,57 @@ void dmaInit(void) {
*
* @special
*/
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
osalDbgCheck(dmastp != NULL);
osalDbgCheck(stp != NULL);
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U)
if ((dma.streams_mask & (1U << stp->selfindex)) != 0U)
return true;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].func = func;
dma_isr_redir[dmastp->selfindex].param = param;
dma_streams_mask |= (1U << dmastp->selfindex);
dma.isr_redir[stp->selfindex].func = func;
dma.isr_redir[stp->selfindex].param = param;
dma.streams_mask |= (1U << stp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
rccEnableDMA1(false);
}
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
rccEnableDMA2(false);
}
/* Putting the stream in a safe state.*/
dmaStreamDisable(dmastp);
dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
dmaStreamDisable(stp);
stp->stream->CR = STM32_DMA_CR_RESET_VALUE;
stp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) {
nvicEnableVector(dmastp->vector, priority);
nvicEnableVector(stp->vector, priority);
}
return false;
}
/**
* @brief Associates a peripheral request to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] per peripheral identifier
*
* @special
*/
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per) {
osalDbgCheck(per < 256U);
dmastp->mux->CCR = per;
stp->mux->CCR = per;
}
/**
@ -507,29 +511,33 @@ void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
void dmaStreamRelease(const stm32_dma_stream_t *stp) {
osalDbgCheck(dmastp != NULL);
osalDbgCheck(stp != NULL);
/* Check if the streams is not taken.*/
osalDbgAssert((dma_streams_mask & (1U << dmastp->selfindex)) != 0U,
osalDbgAssert((dma.streams_mask & (1U << stp->selfindex)) != 0U,
"not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
nvicDisableVector(stp->vector);
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1U << dmastp->selfindex);
dma.streams_mask &= ~(1U << stp->selfindex);
/* Clearing associated handler and parameter.*/
dma.isr_redir->func = NULL;
dma.isr_redir->param = NULL;
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1();
}
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2();
}
}

114
os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h
View File

@ -44,8 +44,8 @@
/**
* @brief Checks if a DMA priority is within the valid range.
* @param[in] prio DMA priority
*
* @param[in] prio DMA priority
* @retval The check result.
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
@ -54,8 +54,8 @@
/**
* @brief Checks if a DMA channel is within the valid range.
* @param[in] ch DMA channel
*
* @param[in] ch DMA channel
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
@ -67,7 +67,7 @@
* @{
*/
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
* @brief Returns a pointer to a @p stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
@ -416,13 +416,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the PAR register
*
* @special
*/
#define dmaStreamSetPeripheral(dmastp, addr) { \
(dmastp)->stream->PAR = (uint32_t)(addr); \
#define dmaStreamSetPeripheral(stp, addr) { \
(stp)->stream->PAR = (uint32_t)(addr); \
}
/**
@ -431,26 +431,26 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the M0AR register
*
* @special
*/
#define dmaStreamSetMemory0(dmastp, addr) { \
(dmastp)->stream->M0AR = (uint32_t)(addr); \
#define dmaStreamSetMemory0(stp, addr) { \
(stp)->stream->M0AR = (uint32_t)(addr); \
}
/**
* @brief Associates an alternate memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the M1AR register
*
* @special
*/
#define dmaStreamSetMemory1(dmastp, addr) { \
(dmastp)->stream->M1AR = (uint32_t)(addr); \
#define dmaStreamSetMemory1(stp, addr) { \
(stp)->stream->M1AR = (uint32_t)(addr); \
}
/**
@ -459,13 +459,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define dmaStreamSetTransactionSize(dmastp, size) { \
(dmastp)->stream->NDTR = (uint32_t)(size); \
#define dmaStreamSetTransactionSize(stp, size) { \
(stp)->stream->NDTR = (uint32_t)(size); \
}
/**
@ -474,12 +474,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @return The number of transfers to be performed.
*
* @special
*/
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
#define dmaStreamGetTransactionSize(stp) ((size_t)((stp)->stream->NDTR))
/**
* @brief Programs the stream mode settings.
@ -487,13 +487,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the CR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->stream->CR = (uint32_t)(mode); \
#define dmaStreamSetMode(stp, mode) { \
(stp)->stream->CR = (uint32_t)(mode); \
}
/**
@ -502,13 +502,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the FCR register
*
* @special
*/
#define dmaStreamSetFIFO(dmastp, mode) { \
(dmastp)->stream->FCR = (uint32_t)(mode); \
#define dmaStreamSetFIFO(stp, mode) { \
(stp)->stream->FCR = (uint32_t)(mode); \
}
/**
@ -517,12 +517,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamEnable(dmastp) { \
(dmastp)->stream->CR |= STM32_DMA_CR_EN; \
#define dmaStreamEnable(stp) { \
(stp)->stream->CR |= STM32_DMA_CR_EN; \
}
/**
@ -535,17 +535,17 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_EN); \
while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
#define dmaStreamDisable(stp) { \
(stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_EN); \
while (((stp)->stream->CR & STM32_DMA_CR_EN) != 0) \
; \
dmaStreamClearInterrupt(dmastp); \
dmaStreamClearInterrupt(stp); \
}
/**
@ -554,12 +554,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
#define dmaStreamClearInterrupt(stp) { \
*(stp)->ifcr = STM32_DMA_ISR_MASK << (stp)->ishift; \
}
/**
@ -569,7 +569,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_DMA_CR_MINC
@ -581,14 +581,14 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @param[in] dst destination address
* @param[in] n number of data units to copy
*/
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
dmaStreamSetPeripheral(dmastp, src); \
dmaStreamSetMemory0(dmastp, dst); \
dmaStreamSetTransactionSize(dmastp, n); \
dmaStreamSetMode(dmastp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
STM32_DMA_CR_DIR_M2M); \
dmaStreamEnable(dmastp); \
#define dmaStartMemCopy(stp, mode, src, dst, n) { \
dmaStreamSetPeripheral(stp, src); \
dmaStreamSetMemory0(stp, dst); \
dmaStreamSetTransactionSize(stp, n); \
dmaStreamSetMode(stp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
STM32_DMA_CR_DIR_M2M); \
dmaStreamEnable(stp); \
}
/**
@ -596,14 +596,14 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
*/
#define dmaWaitCompletion(dmastp) { \
(dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
while ((dmastp)->stream->CR & STM32_DMA_CR_EN) \
#define dmaWaitCompletion(stp) { \
(stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
while ((stp)->stream->CR & STM32_DMA_CR_EN) \
; \
dmaStreamClearInterrupt(dmastp); \
dmaStreamClearInterrupt(stp); \
}
/**
@ -612,13 +612,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @return Current memory target index.
*
* @special
*/
#define dmaStreamGetCurrentTarget(dmastp) \
(((dmastp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U)
#define dmaStreamGetCurrentTarget(stp) \
(((stp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U)
/** @} */
/*===========================================================================*/
@ -633,12 +633,12 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
extern "C" {
#endif
void dmaInit(void);
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per);
void dmaStreamRelease(const stm32_dma_stream_t *stp);
#ifdef __cplusplus
}
#endif

385
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
View File

@ -96,8 +96,8 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
spip->spi->CR1 |= SPI_CR1_CSUSP;
/* Stop everything.*/
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
dmaStreamDisable(spip->tx.dma);
dmaStreamDisable(spip->rx.dma);
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
@ -284,8 +284,9 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL);
SPID1.is_bdma = false;
SPID1.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL);
SPID1.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL);
SPID1.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@ -303,8 +304,9 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL);
SPID2.is_bdma = false;
SPID2.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL);
SPID2.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL);
SPID2.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@ -322,8 +324,9 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_CHANNEL);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_CHANNEL);
SPID3.is_bdma = false;
SPID3.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_CHANNEL);
SPID3.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_CHANNEL);
SPID3.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@ -341,8 +344,9 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_CHANNEL);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_CHANNEL);
SPID4.is_bdma = false;
SPID4.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_CHANNEL);
SPID4.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_CHANNEL);
SPID4.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@ -360,8 +364,9 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_CHANNEL);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_CHANNEL);
SPID5.is_bdma = false;
SPID5.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_CHANNEL);
SPID5.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_CHANNEL);
SPID5.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@ -379,17 +384,16 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
SPID6.dmarx = STM32_BDMA_STREAM(STM32_SPI_SPI6_RX_BDMA_CHANNEL);
SPID6.dmatx = STM32_BDMA_STREAM(STM32_SPI_SPI6_TX_BDMA_CHANNEL);
SPID6.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.is_bdma = true;
SPID6.rx.bdma = STM32_BDMA_STREAM(STM32_SPI_SPI6_RX_BDMA_CHANNEL);
SPID6.tx.bdma = STM32_BDMA_STREAM(STM32_SPI_SPI6_TX_BDMA_CHANNEL);
SPID6.rxdmamode = STM32_BDMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_BDMA_CR_DIR_P2M |
STM32_BDMA_CR_TCIE |
STM32_BDMA_CR_TEIE;
SPID6.txdmamode = STM32_BDMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_BDMA_CR_DIR_M2P |
STM32_BDMA_CR_TEIE;
#if !defined(STM32_SPI6_SUPPRESS_ISR)
nvicEnableVector(STM32_SPI6_NUMBER, STM32_SPI_SPI6_IRQ_PRIORITY);
#endif
@ -404,158 +408,205 @@ void spi_lld_init(void) {
* @notapi
*/
void spi_lld_start(SPIDriver *spip) {
uint32_t dsize, cfg1;
uint32_t dsize;
/* If in stopped state then enables the SPI and DMA clocks.*/
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = dmaStreamAllocate(spip->rx.dma,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = dmaStreamAllocate(spip->tx.dma,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI1_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX1_SPI1_TX);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI1_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI1_TX);
}
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = dmaStreamAllocate(spip->rx.dma,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = dmaStreamAllocate(spip->tx.dma,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI2_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX1_SPI2_TX);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI2_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI2_TX);
}
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = dmaStreamAllocate(spip->rx.dma,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = dmaStreamAllocate(spip->tx.dma,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI3_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX1_SPI3_TX);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI3_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI3_TX);
}
#endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = dmaStreamAllocate(spip->rx.dma,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = dmaStreamAllocate(spip->tx.dma,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI4(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI4_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX1_SPI4_TX);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI4_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI4_TX);
}
#endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = dmaStreamAllocate(spip->rx.dma,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = dmaStreamAllocate(spip->tx.dma,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI5(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI5_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX1_SPI5_TX);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI5_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI5_TX);
}
#endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
b = bdmaStreamAllocate(spip->rx.bdma,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(stm32_bdmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
b = bdmaStreamAllocate(spip->tx.bdma,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(stm32_bdmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI6(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX2_SPI6_RX);
dmaSetRequestSource(spip->dmatx, STM32_DMAMUX2_SPI6_TX);
bdmaSetRequestSource(spip->rx.bdma, STM32_DMAMUX2_SPI6_RX);
bdmaSetRequestSource(spip->tx.bdma, STM32_DMAMUX2_SPI6_TX);
}
#endif
/* DMA setup.*/
dmaStreamSetPeripheral(spip->dmarx, &spip->spi->RXDR);
dmaStreamSetPeripheral(spip->dmatx, &spip->spi->TXDR);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamSetPeripheral(spip->rx.bdma, &spip->spi->RXDR);
bdmaStreamSetPeripheral(spip->tx.bdma, &spip->spi->TXDR);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamSetPeripheral(spip->rx.dma, &spip->spi->RXDR);
dmaStreamSetPeripheral(spip->tx.dma, &spip->spi->TXDR);
}
#endif
}
/* Configuration-specific DMA setup.*/
dsize = (spip->config->cfg1 & SPI_CFG1_DSIZE_Msk) + 1U;
cfg1 = spip->config->cfg1 | SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN;
cfg1 &= ~SPI_CFG1_FTHLV_Msk;
if (dsize <= 8U) {
/* Frame width is between 4 and 8 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
cfg1 |= SPI_CFG1_FTHLV_VALUE(0);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
if (dsize <= 8U) {
/* Frame width is between 4 and 8 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_BYTE | STM32_BDMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_BYTE | STM32_BDMA_CR_MSIZE_BYTE;
}
else if (dsize <= 16U) {
/* Frame width is between 9 and 16 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_HWORD | STM32_BDMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_HWORD | STM32_BDMA_CR_MSIZE_HWORD;
}
else {
/* Frame width is between 16 and 32 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_WORD | STM32_BDMA_CR_MSIZE_WORD;
spip->txdmamode = (spip->txdmamode & ~STM32_BDMA_CR_SIZE_MASK) |
STM32_BDMA_CR_PSIZE_WORD | STM32_BDMA_CR_MSIZE_WORD;
}
}
else if (dsize <= 16U) {
/* Frame width is between 9 and 16 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
cfg1 |= SPI_CFG1_FTHLV_VALUE(0);
}
else {
/* Frame width is between 16 and 32 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
cfg1 |= SPI_CFG1_FTHLV_VALUE(0);
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
if (dsize <= 8U) {
/* Frame width is between 4 and 8 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
}
else if (dsize <= 16U) {
/* Frame width is between 9 and 16 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
}
else {
/* Frame width is between 16 and 32 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
}
}
#endif
/* SPI setup and enable.*/
spip->spi->CR1 &= ~SPI_CR1_SPE;
spip->spi->CR1 = SPI_CR1_MASRX;
spip->spi->CR2 = 0U;
spip->spi->CFG1 = cfg1;
spip->spi->CFG1 = (spip->config->cfg1 & ~SPI_CFG1_FTHLV_Msk) |
SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN;
spip->spi->CFG2 = (spip->config->cfg2 | SPI_CFG2_MASTER | SPI_CFG2_SSOE) &
~SPI_CFG2_COMM_Msk;
spip->spi->IER = SPI_IER_OVRIE;
@ -582,8 +633,24 @@ void spi_lld_stop(SPIDriver *spip) {
spip->spi->CFG1 = 0U;
spip->spi->CFG2 = 0U;
spip->spi->IER = 0U;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamRelease(spip->rx.bdma);
bdmaStreamRelease(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamRelease(spip->rx.dma);
dmaStreamRelease(spip->tx.dma);
}
#endif
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip)
@ -654,16 +721,40 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamSetMemory(spip->rx.bdma, &dummyrx);
bdmaStreamSetTransactionSize(spip->rx.bdma, n);
bdmaStreamSetMode(spip->rx.bdma, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
bdmaStreamSetMemory(spip->tx.bdma, &dummytx);
bdmaStreamSetTransactionSize(spip->tx.bdma, n);
bdmaStreamSetMode(spip->tx.bdma, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
bdmaStreamEnable(spip->rx.bdma);
bdmaStreamEnable(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamSetMemory0(spip->rx.dma, &dummyrx);
dmaStreamSetTransactionSize(spip->rx.dma, n);
dmaStreamSetMode(spip->rx.dma, spip->rxdmamode);
dmaStreamSetMemory0(spip->tx.dma, &dummytx);
dmaStreamSetTransactionSize(spip->tx.dma, n);
dmaStreamSetMode(spip->tx.dma, spip->txdmamode);
dmaStreamEnable(spip->rx.dma);
dmaStreamEnable(spip->tx.dma);
}
#endif
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -688,16 +779,40 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamSetMemory(spip->rx.bdma, rxbuf);
bdmaStreamSetTransactionSize(spip->rx.bdma, n);
bdmaStreamSetMode(spip->rx.bdma, spip->rxdmamode | STM32_BDMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
bdmaStreamSetMemory(spip->tx.bdma, txbuf);
bdmaStreamSetTransactionSize(spip->tx.bdma, n);
bdmaStreamSetMode(spip->tx.bdma, spip->txdmamode | STM32_BDMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
bdmaStreamEnable(spip->rx.bdma);
bdmaStreamEnable(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamSetMemory0(spip->rx.dma, rxbuf);
dmaStreamSetTransactionSize(spip->rx.dma, n);
dmaStreamSetMode(spip->rx.dma, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->tx.dma, txbuf);
dmaStreamSetTransactionSize(spip->tx.dma, n);
dmaStreamSetMode(spip->tx.dma, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->rx.dma);
dmaStreamEnable(spip->tx.dma);
}
#endif
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -719,16 +834,40 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamSetMemory(spip->rx.bdma, &dummyrx);
bdmaStreamSetTransactionSize(spip->rx.bdma, n);
bdmaStreamSetMode(spip->rx.bdma, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
bdmaStreamSetMemory(spip->tx.bdma, txbuf);
bdmaStreamSetTransactionSize(spip->tx.bdma, n);
bdmaStreamSetMode(spip->tx.bdma, spip->txdmamode | STM32_BDMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
bdmaStreamEnable(spip->rx.bdma);
bdmaStreamEnable(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamSetMemory0(spip->rx.dma, &dummyrx);
dmaStreamSetTransactionSize(spip->rx.dma, n);
dmaStreamSetMode(spip->rx.dma, spip->rxdmamode);
dmaStreamSetMemory0(spip->tx.dma, txbuf);
dmaStreamSetTransactionSize(spip->tx.dma, n);
dmaStreamSetMode(spip->tx.dma, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->rx.dma);
dmaStreamEnable(spip->tx.dma);
}
#endif
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -750,16 +889,40 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma)
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamSetMemory(spip->rx.bdma, rxbuf);
bdmaStreamSetTransactionSize(spip->rx.bdma, n);
bdmaStreamSetMode(spip->rx.bdma, spip->rxdmamode | STM32_BDMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
bdmaStreamSetMemory(spip->tx.bdma, &dummytx);
bdmaStreamSetTransactionSize(spip->tx.bdma, n);
bdmaStreamSetMode(spip->tx.bdma, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
bdmaStreamEnable(spip->rx.bdma);
bdmaStreamEnable(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
else
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamSetMemory0(spip->rx.dma, rxbuf);
dmaStreamSetTransactionSize(spip->rx.dma, n);
dmaStreamSetMode(spip->rx.dma, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->tx.dma, &dummytx);
dmaStreamSetTransactionSize(spip->tx.dma, n);
dmaStreamSetMode(spip->tx.dma, spip->txdmamode);
dmaStreamEnable(spip->rx.dma);
dmaStreamEnable(spip->tx.dma);
}
#endif
spip->spi->CR1 |= SPI_CR1_CSTART;
}

46
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
View File

@ -478,10 +478,14 @@
#if STM32_SPI_USE_SPI1 | STM32_SPI_USE_SPI2 | STM32_SPI_USE_SPI1 | \
STM32_SPI_USE_SPI4 | STM32_SPI_USE_SPI5
#define STM32_SPI_DMA_REQUIRED
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
#elif STM32_SPI_USE_SPI6
#endif
#if STM32_SPI_USE_SPI6
#define STM32_SPI_BDMA_REQUIRED
#if !defined(STM32_BDMA_REQUIRED)
#define STM32_BDMA_REQUIRED
#endif
@ -585,14 +589,46 @@ struct SPIDriver {
* @brief Pointer to the SPIx registers block.
*/
SPI_TypeDef *spi;
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
/**
* @brief Receive DMA stream.
* @brief DMA type for this instance.
*/
const stm32_dma_stream_t *dmarx;
bool is_bdma;
#endif
/**
* @brief Transmit DMA stream.
* @brief Union of the RX DMA streams.
*/
const stm32_dma_stream_t *dmatx;
union {
#if defined(STM32_SPI_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Receive DMA stream.
*/
const stm32_dma_stream_t *dma;
#endif
#if defined(STM32_SPI_BDMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Receive BDMA stream.
*/
const stm32_bdma_stream_t *bdma;
#endif
} rx;
/**
* @brief Union of the TX DMA streams.
*/
union {
#if defined(STM32_SPI_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Transmit DMA stream.
*/
const stm32_dma_stream_t *dma;
#endif
#if defined(STM32_SPI_BDMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief Transmit DMA stream.
*/
const stm32_bdma_stream_t *bdma;
#endif
} tx;
/**
* @brief RX DMA mode bit mask.
*/

3
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -141,6 +141,9 @@ void hal_lld_init(void) {
rccResetAPB4(~0);
/* DMA subsystems initialization.*/
#if defined(STM32_BDMA_REQUIRED)
bdmaInit();
#endif
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif

1
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -2877,6 +2877,7 @@
#include "mpu.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_bdma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus

1
os/hal/ports/STM32/STM32H7xx/platform.mk
View File

@ -21,6 +21,7 @@ else
endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/driver.mk

23
os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
View File

@ -499,6 +499,29 @@
* @name DMA peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the BDMA1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableBDMA1(lp) rccEnableAHB4(RCC_AHB4ENR_BDMAEN, lp)
/**
* @brief Disables the BDMA1 peripheral clock.
*
* @api
*/
#define rccDisableBDMA1() rccDisableAHB4(RCC_AHB4ENR_BDMAEN)
/**
* @brief Resets the BDMA1 peripheral.
*
* @api
*/
#define rccResetBDMA1() rccEnableAHB4(RCC_AHB4RSTR_BDMARST)
/**
* @brief Enables the DMA1 peripheral clock.
*

19
os/hal/ports/STM32/STM32H7xx/stm32_registry.h
View File

@ -67,6 +67,25 @@
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* BDMA attributes.*/
#define STM32_HAS_BDMA1 TRUE
#define STM32_BDMA1_CH0_HANDLER Vector244
#define STM32_BDMA1_CH1_HANDLER Vector248
#define STM32_BDMA1_CH2_HANDLER Vector24C
#define STM32_BDMA1_CH3_HANDLER Vector250
#define STM32_BDMA1_CH4_HANDLER Vector254
#define STM32_BDMA1_CH5_HANDLER Vector258
#define STM32_BDMA1_CH6_HANDLER Vector25C
#define STM32_BDMA1_CH7_HANDLER Vector260
#define STM32_BDMA1_CH0_NUMBER 129
#define STM32_BDMA1_CH1_NUMBER 130
#define STM32_BDMA1_CH2_NUMBER 131
#define STM32_BDMA1_CH3_NUMBER 132
#define STM32_BDMA1_CH4_NUMBER 133
#define STM32_BDMA1_CH5_NUMBER 134
#define STM32_BDMA1_CH6_NUMBER 135
#define STM32_BDMA1_CH7_NUMBER 136
/* DMA attributes.*/
#define STM32_DMA_CACHE_HANDLING TRUE

2
testhal/STM32/multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h
View File

@ -357,7 +357,7 @@
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_USE_SPI4 TRUE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_USE_SPI6 TRUE
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10