From 4155ce3fa5c395de598246f98468822fc85a82f0 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 21 Oct 2012 17:37:53 +0000
Subject: [PATCH] Fixed bug 3578944.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4771 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F2xx/hal_lld.h | 16 ++++++++--------
 os/hal/platforms/STM32F4xx/hal_lld.h | 10 +++++-----
 readme.txt                           |  2 ++
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index ceafd2a58..095a62f50 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -98,7 +98,7 @@
 #define STM32_PLLIN_MAX         2000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
 #define STM32_PLLIN_MIN         950000
 
@@ -118,7 +118,7 @@
 #define STM32_PLLOUT_MAX        120000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        24000000
 
@@ -659,7 +659,7 @@
 
 /**
  * @brief   PLLQ multiplier value.
- * @note    The allowed values are 4..15.
+ * @note    The allowed values are 2..15.
  * @note    The default value is calculated for a 120MHz system clock from
  *          an external 8MHz HSE clock.
  */
@@ -722,7 +722,7 @@
 
 /**
  * @brief   MC02 clock source value.
- * @note    The default value outputs SYSCLK / 4 on MC02 pin.
+ * @note    The default value outputs SYSCLK / 5 on MC02 pin.
  */
 #if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
 #define STM32_MCO2SEL               STM32_MCO2SEL_SYSCLK
@@ -730,10 +730,10 @@
 
 /**
  * @brief   MC02 prescaler value.
- * @note    The default value outputs SYSCLK / 4 on MC02 pin.
+ * @note    The default value outputs SYSCLK / 5 on MC02 pin.
  */
 #if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
-#define STM32_MCO2PRE               STM32_MCO2PRE_DIV4
+#define STM32_MCO2PRE               STM32_MCO2PRE_DIV5
 #endif
 
 /**
@@ -965,7 +965,7 @@
 /**
  * @brief   STM32_PLLN field.
  */
-#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) ||             \
+#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) ||              \
     defined(__DOXYGEN__)
 #define STM32_PLLN                  (STM32_PLLN_VALUE << 6)
 #else
@@ -990,7 +990,7 @@
 /**
  * @brief   STM32_PLLQ field.
  */
-#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) ||                \
+#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \
     defined(__DOXYGEN__)
 #define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)
 #else
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index b6ac2025d..c97ce41fa 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -93,7 +93,7 @@
 #define STM32_PLLIN_MAX         2000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
 #define STM32_PLLIN_MIN         950000
 
@@ -113,7 +113,7 @@
 #define STM32_PLLOUT_MAX        168000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        24000000
 
@@ -669,7 +669,7 @@
 
 /**
  * @brief   PLLQ multiplier value.
- * @note    The allowed values are 4..15.
+ * @note    The allowed values are 2..15.
  * @note    The default value is calculated for a 168MHz system clock from
  *          an external 8MHz HSE clock.
  */
@@ -985,7 +985,7 @@
 /**
  * @brief   STM32_PLLN field.
  */
-#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) ||             \
+#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) ||              \
     defined(__DOXYGEN__)
 #define STM32_PLLN                  (STM32_PLLN_VALUE << 6)
 #else
@@ -1010,7 +1010,7 @@
 /**
  * @brief   STM32_PLLQ field.
  */
-#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) ||                \
+#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \
     defined(__DOXYGEN__)
 #define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)
 #else
diff --git a/readme.txt b/readme.txt
index f6cc69e80..b43e9cece 100644
--- a/readme.txt
+++ b/readme.txt
@@ -79,6 +79,8 @@
 *****************************************************************************
 
 *** 2.4.3 ***
+- FIX: Fixed various typos and wrong limits in the STM32F4/F2 HAL driver
+  (bug 3578944).
 - FIX: Fixed ARM CMx crt0.c fails at low optimization levels (bug 3578927).
 - FIX: Fixed compilation issue in syscalls.c (bug 3576771).
 - FIX: Fixed superfluous pack #defines cause nasty warning (bug 3575662).