git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14410 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
33df3af7ab
commit
42a5b3f8db
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@ -34,270 +34,6 @@
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* @{
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*/
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/* RCC attributes.*/
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#define STM32_RCC_HAS_HSI16 TRUE
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/*#define STM32_RCC_HAS_HSI48 TRUE*/ /* See below, it changes.*/
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#define STM32_RCC_HAS_MSI TRUE
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#define STM32_RCC_HAS_LSI TRUE
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#define STM32_RCC_HAS_LSI_PRESCALER FALSE
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#define STM32_RCC_HAS_LSE TRUE
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#define STM32_RCC_HAS_HSE TRUE
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#define STM32_RCC_HAS_PLL TRUE
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#define STM32_RCC_PLL_HAS_P TRUE
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#define STM32_RCC_PLL_HAS_Q TRUE
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#define STM32_RCC_PLL_HAS_R TRUE
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#define STM32_RCC_HAS_PLLSAI1 TRUE
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#define STM32_RCC_PLLSAI1_HAS_P TRUE
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#define STM32_RCC_PLLSAI1_HAS_Q TRUE
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#define STM32_RCC_PLLSAI1_HAS_R TRUE
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#define STM32_RCC_HAS_PLLSAI2 TRUE
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#define STM32_RCC_PLLSAI2_HAS_P TRUE
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#define STM32_RCC_PLLSAI2_HAS_Q FALSE
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#define STM32_RCC_PLLSAI2_HAS_R TRUE
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/*===========================================================================*/
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/* STM32L422xx */
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/*===========================================================================*/
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#if defined(STM32L422xx) || defined(__DOXYGEN__)
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0003
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#define STM32_TAMP_CR2_MASK 0x030300FF
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#define STM32_TAMP_FLTCR_MASK 0x000000FF
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#define STM32_TAMP_IER_MASK 0x003C0003
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/* Clock attributes.*/
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#define STM32_RCC_HAS_HSI48 TRUE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 FALSE
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#define STM32_HAS_DAC1_CH2 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX FALSE
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#define STM32_DMA_SUPPORTS_CSELR TRUE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA2_NUM_CHANNELS 7
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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/* TODO à verifier */
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#define STM32_EXTI_NUM_LINES 40
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#define STM32_EXTI_IMR1_MASK 0xFF820000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 1
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#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
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#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
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#endif
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD FALSE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_I2C1_RX_DMA_CHN 0x03500000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_I2C1_TX_DMA_CHN 0x05300000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C3_TX_DMA_CHN 0x00000030
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_QUADSPI1_DMA_CHN 0x03050000
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 FALSE
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#define STM32_HAS_SDMMC2 FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI1_RX_DMA_CHN 0x00000410
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI1_TX_DMA_CHN 0x00004100
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2/* SPI attributes. */
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#define STM32_HAS_SPIR FALSE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM3 FALSE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART1_RX_DMA_CHN 0x02020000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_USART1_TX_DMA_CHN 0x00202000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_RX_DMA_CHN 0x00200000
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_USART2_TX_DMA_CHN 0x02000000
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
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#define STM32_USB_PMA_SIZE 1024
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#define STM32_USB_HAS_BCDR TRUE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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#endif /* defined(STM32L422xx) */
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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@ -345,7 +81,28 @@
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#if defined(STM32L432xx) || defined(__DOXYGEN__)
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/* RCC attributes.*/
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#define STM32_RCC_HAS_HSI16 TRUE
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#define STM32_RCC_HAS_HSI48 TRUE
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#define STM32_RCC_HAS_MSI TRUE
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#define STM32_RCC_HAS_LSI TRUE
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#define STM32_RCC_HAS_LSI_PRESCALER FALSE
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#define STM32_RCC_HAS_LSE TRUE
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#define STM32_RCC_HAS_HSE TRUE
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#define STM32_RCC_HAS_PLL TRUE
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#define STM32_RCC_PLL_HAS_P TRUE
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#define STM32_RCC_PLL_HAS_Q TRUE
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#define STM32_RCC_PLL_HAS_R TRUE
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#define STM32_RCC_HAS_PLLSAI1 TRUE
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#define STM32_RCC_PLLSAI1_HAS_P TRUE
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#define STM32_RCC_PLLSAI1_HAS_Q TRUE
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#define STM32_RCC_PLLSAI1_HAS_R TRUE
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#define STM32_RCC_HAS_PLLSAI2 FALSE
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#define STM32_RCC_PLLSAI2_HAS_P FALSE
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#define STM32_RCC_PLLSAI2_HAS_Q FALSE
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#define STM32_RCC_PLLSAI2_HAS_R FALSE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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@ -560,6 +317,264 @@
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#endif /* defined(STM32L432xx) */
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/*===========================================================================*/
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/* STM32L422xx */
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/*===========================================================================*/
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#if defined(STM32L422xx) || defined(__DOXYGEN__)
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0003
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#define STM32_TAMP_CR2_MASK 0x030300FF
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#define STM32_TAMP_FLTCR_MASK 0x000000FF
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#define STM32_TAMP_IER_MASK 0x003C0003
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/* RCC attributes.*/
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#define STM32_RCC_HAS_HSI16 TRUE
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#define STM32_RCC_HAS_HSI48 TRUE
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#define STM32_RCC_HAS_MSI TRUE
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#define STM32_RCC_HAS_LSI TRUE
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#define STM32_RCC_HAS_LSI_PRESCALER FALSE
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#define STM32_RCC_HAS_LSE TRUE
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#define STM32_RCC_HAS_HSE TRUE
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#define STM32_RCC_HAS_PLL TRUE
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#define STM32_RCC_PLL_HAS_P TRUE
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#define STM32_RCC_PLL_HAS_Q TRUE
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#define STM32_RCC_PLL_HAS_R TRUE
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#define STM32_RCC_HAS_PLLSAI1 FALSE
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#define STM32_RCC_PLLSAI1_HAS_P FALSE
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#define STM32_RCC_PLLSAI1_HAS_Q FALSE
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#define STM32_RCC_PLLSAI1_HAS_R FALSE
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#define STM32_RCC_HAS_PLLSAI2 FALSE
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#define STM32_RCC_PLLSAI2_HAS_P FALSE
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#define STM32_RCC_PLLSAI2_HAS_Q FALSE
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#define STM32_RCC_PLLSAI2_HAS_R FALSE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 FALSE
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#define STM32_HAS_DAC1_CH2 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX FALSE
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#define STM32_DMA_SUPPORTS_CSELR TRUE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA2_NUM_CHANNELS 7
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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/* TODO à verifier */
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#define STM32_EXTI_NUM_LINES 40
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#define STM32_EXTI_IMR1_MASK 0xFF820000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 1
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#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
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#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
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#endif
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD FALSE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
|
||||
RCC_AHB2ENR_GPIOBEN | \
|
||||
RCC_AHB2ENR_GPIOCEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x03500000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x05300000
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
||||
#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000030
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C4 FALSE
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 TRUE
|
||||
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_QUADSPI1_DMA_CHN 0x03050000
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 FALSE
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000410
|
||||
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00004100
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2/* SPI attributes. */
|
||||
#define STM32_HAS_SPIR FALSE
|
||||
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM3 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x02020000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00202000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00200000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x02000000
|
||||
|
||||
#define STM32_HAS_LPUART1 TRUE
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
||||
#define STM32_USB_PMA_SIZE 1024
|
||||
#define STM32_USB_HAS_BCDR TRUE
|
||||
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
|
||||
#endif /* defined(STM32L422xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32L433xx, STM32L443xx. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -567,7 +582,28 @@
|
|||
#if defined(STM32L433xx) || defined(STM32L443xx) || defined(__DOXYGEN__)
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_HAS_HSI16 TRUE
|
||||
#define STM32_RCC_HAS_HSI48 TRUE
|
||||
#define STM32_RCC_HAS_MSI TRUE
|
||||
#define STM32_RCC_HAS_LSI TRUE
|
||||
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
|
||||
#define STM32_RCC_HAS_LSE TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLL TRUE
|
||||
#define STM32_RCC_PLL_HAS_P TRUE
|
||||
#define STM32_RCC_PLL_HAS_Q TRUE
|
||||
#define STM32_RCC_PLL_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI1 TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_Q TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI2 FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_P FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_Q FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_R FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
|
|
@ -810,7 +846,28 @@
|
|||
#if defined(STM32L452xx) || defined(__DOXYGEN__)
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_HAS_HSI16 TRUE
|
||||
#define STM32_RCC_HAS_HSI48 TRUE
|
||||
#define STM32_RCC_HAS_MSI TRUE
|
||||
#define STM32_RCC_HAS_LSI TRUE
|
||||
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
|
||||
#define STM32_RCC_HAS_LSE TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLL TRUE
|
||||
#define STM32_RCC_PLL_HAS_P TRUE
|
||||
#define STM32_RCC_PLL_HAS_Q TRUE
|
||||
#define STM32_RCC_PLL_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI1 TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_Q TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI2 FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_P FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_Q FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_R FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
|
|
@ -1054,7 +1111,28 @@
|
|||
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L486xx)
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_HAS_HSI16 TRUE
|
||||
#define STM32_RCC_HAS_HSI48 FALSE
|
||||
#define STM32_RCC_HAS_MSI TRUE
|
||||
#define STM32_RCC_HAS_LSI TRUE
|
||||
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
|
||||
#define STM32_RCC_HAS_LSE TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLL TRUE
|
||||
#define STM32_RCC_PLL_HAS_P TRUE
|
||||
#define STM32_RCC_PLL_HAS_Q TRUE
|
||||
#define STM32_RCC_PLL_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI1 TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_Q TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI2 TRUE
|
||||
#define STM32_RCC_PLLSAI2_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI2_HAS_Q FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_R TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
|
|
@ -1334,7 +1412,28 @@
|
|||
#if defined(STM32L496xx) || defined(STM32L4A6xx)
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_HAS_HSI16 TRUE
|
||||
#define STM32_RCC_HAS_HSI48 FALSE
|
||||
#define STM32_RCC_HAS_MSI TRUE
|
||||
#define STM32_RCC_HAS_LSI TRUE
|
||||
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
|
||||
#define STM32_RCC_HAS_LSE TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLL TRUE
|
||||
#define STM32_RCC_PLL_HAS_P TRUE
|
||||
#define STM32_RCC_PLL_HAS_Q TRUE
|
||||
#define STM32_RCC_PLL_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI1 TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_Q TRUE
|
||||
#define STM32_RCC_PLLSAI1_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI2 TRUE
|
||||
#define STM32_RCC_PLLSAI2_HAS_P TRUE
|
||||
#define STM32_RCC_PLLSAI2_HAS_Q FALSE
|
||||
#define STM32_RCC_PLLSAI2_HAS_R TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
|
|
|
|||
Loading…
Reference in New Issue