diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
index 30da7cf7e..25fb6389d 100644
--- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h
+++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
@@ -65,6 +65,128 @@
#define SPC5_SIUL_NUM_PADSELS 44
/** @} */
+/* FlexPWM attributes.*/
+#define SPC5_HAS_FLEXPWM0 TRUE
+#define SPC5_FLEXPWM0_PCTL 41
+#define SPC5_FLEXPWM0_RF0_HANDLER vector179
+#define SPC5_FLEXPWM0_COF0_HANDLER vector180
+#define SPC5_FLEXPWM0_CAF0_HANDLER vector181
+#define SPC5_FLEXPWM0_RF1_HANDLER vector182
+#define SPC5_FLEXPWM0_COF1_HANDLER vector183
+#define SPC5_FLEXPWM0_CAF1_HANDLER vector184
+#define SPC5_FLEXPWM0_RF2_HANDLER vector185
+#define SPC5_FLEXPWM0_COF2_HANDLER vector186
+#define SPC5_FLEXPWM0_CAF2_HANDLER vector187
+#define SPC5_FLEXPWM0_RF3_HANDLER vector188
+#define SPC5_FLEXPWM0_COF3_HANDLER vector189
+#define SPC5_FLEXPWM0_CAF3_HANDLER vector190
+#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191
+#define SPC5_FLEXPWM0_REF_HANDLER vector192
+#define SPC5_FLEXPWM0_RF0_NUMBER 179
+#define SPC5_FLEXPWM0_COF0_NUMBER 180
+#define SPC5_FLEXPWM0_CAF0_NUMBER 181
+#define SPC5_FLEXPWM0_RF1_NUMBER 182
+#define SPC5_FLEXPWM0_COF1_NUMBER 183
+#define SPC5_FLEXPWM0_CAF1_NUMBER 184
+#define SPC5_FLEXPWM0_RF2_NUMBER 185
+#define SPC5_FLEXPWM0_COF2_NUMBER 186
+#define SPC5_FLEXPWM0_CAF2_NUMBER 187
+#define SPC5_FLEXPWM0_RF3_NUMBER 188
+#define SPC5_FLEXPWM0_COF3_NUMBER 189
+#define SPC5_FLEXPWM0_CAF3_NUMBER 190
+#define SPC5_FLEXPWM0_FFLAG_NUMBER 191
+#define SPC5_FLEXPWM0_REF_NUMBER 192
+#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_FLEXPWM1 TRUE
+#define SPC5_FLEXPWM1_PCTL 42
+#define SPC5_FLEXPWM1_RF0_HANDLER vector233
+#define SPC5_FLEXPWM1_COF0_HANDLER vector234
+#define SPC5_FLEXPWM1_CAF0_HANDLER vector235
+#define SPC5_FLEXPWM1_RF1_HANDLER vector236
+#define SPC5_FLEXPWM1_COF1_HANDLER vector237
+#define SPC5_FLEXPWM1_CAF1_HANDLER vector238
+#define SPC5_FLEXPWM1_RF2_HANDLER vector239
+#define SPC5_FLEXPWM1_COF2_HANDLER vector240
+#define SPC5_FLEXPWM1_CAF2_HANDLER vector241
+#define SPC5_FLEXPWM1_RF3_HANDLER vector242
+#define SPC5_FLEXPWM1_COF3_HANDLER vector243
+#define SPC5_FLEXPWM1_CAF3_HANDLER vector244
+#define SPC5_FLEXPWM1_FFLAG_HANDLER vector245
+#define SPC5_FLEXPWM1_REF_HANDLER vector246
+#define SPC5_FLEXPWM1_RF0_NUMBER 233
+#define SPC5_FLEXPWM1_COF0_NUMBER 234
+#define SPC5_FLEXPWM1_CAF0_NUMBER 235
+#define SPC5_FLEXPWM1_RF1_NUMBER 236
+#define SPC5_FLEXPWM1_COF1_NUMBER 237
+#define SPC5_FLEXPWM1_CAF1_NUMBER 238
+#define SPC5_FLEXPWM1_RF2_NUMBER 239
+#define SPC5_FLEXPWM1_COF2_NUMBER 240
+#define SPC5_FLEXPWM1_CAF2_NUMBER 241
+#define SPC5_FLEXPWM1_RF3_NUMBER 242
+#define SPC5_FLEXPWM1_COF3_NUMBER 243
+#define SPC5_FLEXPWM1_CAF3_NUMBER 244
+#define SPC5_FLEXPWM1_FFLAG_NUMBER 245
+#define SPC5_FLEXPWM1_REF_NUMBER 246
+#define SPC5_FLEXPWM1_CLK SPC5_MCONTROL_CLK
+
+/* eTimer attributes.*/
+#define SPC5_HAS_ETIMER0 TRUE
+#define SPC5_ETIMER0_PCTL 38
+#define SPC5_ETIMER0_TC0IR_HANDLER vector157
+#define SPC5_ETIMER0_TC1IR_HANDLER vector158
+#define SPC5_ETIMER0_TC2IR_HANDLER vector159
+#define SPC5_ETIMER0_TC3IR_HANDLER vector160
+#define SPC5_ETIMER0_TC4IR_HANDLER vector161
+#define SPC5_ETIMER0_TC5IR_HANDLER vector162
+#define SPC5_ETIMER0_WTIF_HANDLER vector165
+#define SPC5_ETIMER0_RCF_HANDLER vector167
+#define SPC5_ETIMER0_TC0IR_NUMBER 157
+#define SPC5_ETIMER0_TC1IR_NUMBER 158
+#define SPC5_ETIMER0_TC2IR_NUMBER 159
+#define SPC5_ETIMER0_TC3IR_NUMBER 160
+#define SPC5_ETIMER0_TC4IR_NUMBER 161
+#define SPC5_ETIMER0_TC5IR_NUMBER 162
+#define SPC5_ETIMER0_WTIF_NUMBER 165
+#define SPC5_ETIMER0_RCF_NUMBER 167
+#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_ETIMER1 TRUE
+#define SPC5_ETIMER1_PCTL 39
+#define SPC5_ETIMER1_TC0IR_HANDLER vector168
+#define SPC5_ETIMER1_TC1IR_HANDLER vector169
+#define SPC5_ETIMER1_TC2IR_HANDLER vector170
+#define SPC5_ETIMER1_TC3IR_HANDLER vector171
+#define SPC5_ETIMER1_TC4IR_HANDLER vector172
+#define SPC5_ETIMER1_TC5IR_HANDLER vector173
+#define SPC5_ETIMER1_RCF_HANDLER vector178
+#define SPC5_ETIMER1_TC0IR_NUMBER 168
+#define SPC5_ETIMER1_TC1IR_NUMBER 169
+#define SPC5_ETIMER1_TC2IR_NUMBER 170
+#define SPC5_ETIMER1_TC3IR_NUMBER 171
+#define SPC5_ETIMER1_TC4IR_NUMBER 172
+#define SPC5_ETIMER1_TC5IR_NUMBER 173
+#define SPC5_ETIMER1_RCF_NUMBER 178
+#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_ETIMER2 TRUE
+#define SPC5_ETIMER2_PCTL 40
+#define SPC5_ETIMER2_TC0IR_HANDLER vector222
+#define SPC5_ETIMER2_TC1IR_HANDLER vector223
+#define SPC5_ETIMER2_TC2IR_HANDLER vector224
+#define SPC5_ETIMER2_TC3IR_HANDLER vector225
+#define SPC5_ETIMER2_TC4IR_HANDLER vector226
+#define SPC5_ETIMER2_TC5IR_HANDLER vector227
+#define SPC5_ETIMER2_RCF_HANDLER vector232
+#define SPC5_ETIMER2_TC0IR_NUMBER 222
+#define SPC5_ETIMER2_TC1IR_NUMBER 223
+#define SPC5_ETIMER2_TC2IR_NUMBER 224
+#define SPC5_ETIMER2_TC3IR_NUMBER 225
+#define SPC5_ETIMER2_TC4IR_NUMBER 226
+#define SPC5_ETIMER2_TC5IR_NUMBER 227
+#define SPC5_ETIMER2_RCF_NUMBER 232
+#define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK
+
#endif /* _SPC56EL_REGISTRY_H_ */
/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h
new file mode 100644
index 000000000..b13787a64
--- /dev/null
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h
@@ -0,0 +1,490 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file FlexPWM_v1/flexpwm.h
+ * @brief SPC5xx FlexPWM header file.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _FLEXPWM_H_
+#define _FLEXPWM_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5 FlexPWM registers block.
+ * @note Redefined from the SPC5 headers because the non uniform
+ * declaration of the SubModules registers among the various
+ * sub-families.
+ */
+struct spc5_flexpwm_submodule {
+
+ union {
+ vuint16_t R;
+ } CNT; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ } INIT; /* Initial Count Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DBGEN :1;
+ vuint16_t WAITEN :1;
+ vuint16_t INDEP :1;
+ vuint16_t PWMA_INIT :1;
+ vuint16_t PWMB_INIT :1;
+ vuint16_t PWMX_INIT :1;
+ vuint16_t INIT_SEL :2;
+ vuint16_t FRCEN :1;
+ vuint16_t FORCE :1;
+ vuint16_t FORCE_SEL :3;
+ vuint16_t RELOAD_SEL :1;
+ vuint16_t CLK_SEL :2;
+ } B;
+ } CTRL2; /* Control 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LDFQ :4;
+ vuint16_t HALF :1;
+ vuint16_t FULL :1;
+ vuint16_t DT :2;
+ vuint16_t :1;
+ vuint16_t PRSC :3;
+ vuint16_t :3;
+ vuint16_t DBLEN :1;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ } VAL[6]; /* Value Register 0->5 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACAEN :1;
+ vuint16_t :10;
+ vuint16_t FRACADLY :5;
+ } B;
+ } FRACA; /* Fractional Delay Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACBEN :1;
+ vuint16_t :10;
+ vuint16_t FRACBDLY :5;
+ } B;
+ } FRACB; /* Fractional Delay Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t PWMA_IN :1;
+ vuint16_t PWMB_IN :1;
+ vuint16_t PWMX_IN :1;
+ vuint16_t :2;
+ vuint16_t POLA :1;
+ vuint16_t POLB :1;
+ vuint16_t POLX :1;
+ vuint16_t :2;
+ vuint16_t PWMAFS :2;
+ vuint16_t PWMBFS :2;
+ vuint16_t PWMXFS :2;
+ } B;
+ } OCTRL; /* Output Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t RUF :1;
+ vuint16_t REF :1;
+ vuint16_t RF :1;
+ vuint16_t CFA1 :1;
+ vuint16_t CFA0 :1;
+ vuint16_t CFB1 :1;
+ vuint16_t CFB0 :1;
+ vuint16_t CFX1 :1;
+ vuint16_t CFX0 :1;
+ vuint16_t CMPF :6;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :2;
+ vuint16_t REIE :1;
+ vuint16_t RIE :1;
+ vuint16_t :4;
+ vuint16_t CX1IE :1;
+ vuint16_t CX0IE :1;
+ vuint16_t CMPIE :6;
+ } B;
+ } INTEN; /* Interrupt Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :6;
+ vuint16_t VALDE :1;
+ vuint16_t FAND :1;
+ vuint16_t CAPTDE :2;
+ vuint16_t CA1DE :1;
+ vuint16_t CA0DE :1;
+ vuint16_t CB1DE :1;
+ vuint16_t CB0DE :1;
+ vuint16_t CX1DE :1;
+ vuint16_t CX0DE :1;
+ } B;
+ } DMAEN; /* DMA Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :10;
+ vuint16_t OUT_TRIG_EN :6;
+ } B;
+ } TCTRL; /* Output Trigger Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t DISX :4;
+ vuint16_t DISB :4;
+ vuint16_t DISA :4;
+ } B;
+ } DISMAP; /* Fault Disable Mapping Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t DTCNT0 :11;
+ } B;
+ } DTCNT0; /* Deadtime Count Register 0 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t DTCNT1 :11;
+ } B;
+ } DTCNT1; /* Deadtime Count Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CA1CNT :3;
+ vuint16_t CA0CNT :3;
+ vuint16_t CFAWM :2;
+ vuint16_t EDGCNTAEN :1;
+ vuint16_t INPSELA :1;
+ vuint16_t EDGA1 :2;
+ vuint16_t EDGA0 :2;
+ vuint16_t ONESHOTA :1;
+ vuint16_t ARMA :1;
+ } B;
+ } CAPTCTRLA; /* Capture Control Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTA :8;
+ vuint16_t EDGCMPA :8;
+ } B;
+ } CAPTCOMPA; /* Capture Compare Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CB1CNT :3;
+ vuint16_t CB0CNT :3;
+ vuint16_t CFBWM :2;
+ vuint16_t EDGCNTBEN :1;
+ vuint16_t INPSELB :1;
+ vuint16_t EDGB1 :2;
+ vuint16_t EDGB0 :2;
+ vuint16_t ONESHOTB :1;
+ vuint16_t ARMB :1;
+ } B;
+ } CAPTCTRLB; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTB :8;
+ vuint16_t EDGCMPB :8;
+ } B;
+ } CAPTCOMPB; /* Capture Compare Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CX1CNT :3;
+ vuint16_t CX0CNT :3;
+ vuint16_t CFXWM :2;
+ vuint16_t EDGCNTX_EN :1;
+ vuint16_t INP_SELX :1;
+ vuint16_t EDGX1 :2;
+ vuint16_t EDGX0 :2;
+ vuint16_t ONESHOTX :1;
+ vuint16_t ARMX :1;
+ } B;
+ } CAPTCTRLX; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTX :8;
+ vuint16_t EDGCMPX :8;
+ } B;
+ } CAPTCOMPX; /* Capture Compare Register X */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL0 :16;
+ } B;
+ } CVAL0; /* Capture Value 0 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL0CYC :4;
+ } B;
+ } CVAL0C; /* Capture Value 0 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL1 :16;
+ } B;
+ } CVAL1; /* Capture Value 1 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL1CYC :4;
+ } B;
+ } CVAL1C; /* Capture Value 1 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL2 :16;
+ } B;
+ } CVAL2; /* Capture Value 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL2CYC :4;
+ } B;
+ } CVAL2C; /* Capture Value 2 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL3 :16;
+ } B;
+ } CVAL3; /* Capture Value 3 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL3CYC :4;
+ } B;
+ } CVAL3C; /* Capture Value 3 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL4 :16;
+ } B;
+ } CVAL4; /* Capture Value 4 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL4CYC :4;
+ } B;
+ } CVAL4C; /* Capture Value 4 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL5 :16;
+ } B;
+ } CVAL5; /* Capture Value 5 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL5CYC :4;
+ } B;
+ } CVAL5C; /* Capture Value 5 Cycle Register */
+
+ uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
+
+};
+/* end of FLEXPWM_SUB_tag */
+
+struct spc5_flexpwm {
+
+ struct spc5_flexpwm_submodule SUB[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t PWMA_EN :4;
+ vuint16_t PWMB_EN :4;
+ vuint16_t PWMX_EN :4;
+ } B;
+ } OUTEN; /* Output Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t MASKA :4;
+ vuint16_t MASKB :4;
+ vuint16_t MASKX :4;
+ } B;
+ } MASK; /* Output Mask Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t OUTA_3 :1;
+ vuint16_t OUTB_3 :1;
+ vuint16_t OUTA_2 :1;
+ vuint16_t OUTB_2 :1;
+ vuint16_t OUTA_1 :1;
+ vuint16_t OUTB_1 :1;
+ vuint16_t OUTA_0 :1;
+ vuint16_t OUTB_0 :1;
+ } B;
+ } SWCOUT; /* Software Controlled Output Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SELA_3 :2;
+ vuint16_t SELB_3 :2;
+ vuint16_t SELA_2 :2;
+ vuint16_t SELB_2 :2;
+ vuint16_t SELA_1 :2;
+ vuint16_t SELB_1 :2;
+ vuint16_t SELA_0 :2;
+ vuint16_t SELB_0 :2;
+ } B;
+ } DTSRCSEL; /* Deadtime Source Select Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t IPOL :4;
+ vuint16_t RUN :4;
+ vuint16_t CLDOK :4;
+ vuint16_t LDOK :4;
+ } B;
+ } MCTRL; /* Master Control Register */
+
+ int16_t FLEXPWM_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FLVL :4;
+ vuint16_t FAUTO :4;
+ vuint16_t FSAFE :4;
+ vuint16_t FIE :4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t FTEST :1;
+ vuint16_t FFPIN :4;
+ vuint16_t :4;
+ vuint16_t FFLAG :4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FILT_CNT :3;
+ vuint16_t FILT_PER :8;
+ } B;
+ } FFILT; /* Fault FilterRegister */
+
+};
+/* end of FLEXPWM_tag */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name FlexPWM units references
+ * @{
+ */
+#if SPC5_HAS_FLEXPWM0
+#define SPC5_FLEXPWM_0 (*(volatile struct spc5_flexpwm *)0xFFE24000UL)
+#endif
+
+#if SPC5_HAS_FLEXPWM1
+#define SPC5_FLEXPWM_1 (*(volatile struct spc5_flexpwm *)0xFFE28000UL)
+#endif
+/** @} */
+
+#endif /* _FLEXPWM_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
index ebeb56d66..b3af9845f 100644
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
@@ -449,10 +449,8 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));
}
-#if SPC5_PWM_USE_SMOD0 || SPC5_PWM_USE_SMOD1 || SPC5_PWM_USE_SMOD2 || \
- SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
/**
- * @brief Common SMOD0...SMOD3 IRQ handler.
+ * @brief Common SMOD0...SMOD7 IRQ handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
@@ -599,7 +597,6 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
}
#endif
}
-#endif /* SPC5_PWM_USE_SMOD0 || ... || SPC5_PWM_USE_SMOD7 */
/*===========================================================================*/
/* Driver interrupt handlers. */
@@ -907,7 +904,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD0)
/* Driver initialization.*/
pwmObjectInit(&PWMD1);
- PWMD1.flexpwmp = &FLEXPWM_0;
+ PWMD1.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
@@ -918,7 +915,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD1)
/* Driver initialization.*/
pwmObjectInit(&PWMD2);
- PWMD2.flexpwmp = &FLEXPWM_0;
+ PWMD2.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
@@ -929,7 +926,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD2)
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
- PWMD3.flexpwmp = &FLEXPWM_0;
+ PWMD3.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
@@ -940,7 +937,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD3)
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
- PWMD4.flexpwmp = &FLEXPWM_0;
+ PWMD4.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
@@ -951,7 +948,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD4)
/* Driver initialization.*/
pwmObjectInit(&PWMD5);
- PWMD5.flexpwmp = &FLEXPWM_1;
+ PWMD5.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
@@ -962,7 +959,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD5)
/* Driver initialization.*/
pwmObjectInit(&PWMD6);
- PWMD6.flexpwmp = &FLEXPWM_1;
+ PWMD6.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
@@ -973,7 +970,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD6)
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
- PWMD7.flexpwmp = &FLEXPWM_1;
+ PWMD7.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
@@ -984,7 +981,7 @@ void pwm_lld_init(void) {
#if (SPC5_PWM_USE_SMOD7)
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
- PWMD8.flexpwmp = &FLEXPWM_1;
+ PWMD8.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
index 7bb0d6b83..d51156c90 100644
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
@@ -30,7 +30,7 @@
/*===========================================================================*/
/**
- * @name LINIER register bits definitions
+ * @name STS register bits definitions
* @{
*/
#define SPC5_STS_CMPF0 (1U << 0)
@@ -320,6 +320,7 @@
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
+#include "flexpwm.h"
/**
* @brief PWM mode type.
@@ -409,7 +410,7 @@ struct PWMDriver {
/**
* @Pointer to the volatile FlexPWM registers block.
*/
- volatile struct FLEXPWM_tag *flexpwmp;
+ volatile struct spc5_flexpwm *flexpwmp;
};
/*===========================================================================*/
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h b/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h
new file mode 100644
index 000000000..c0a0f2c76
--- /dev/null
+++ b/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h
@@ -0,0 +1,314 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file eTimer_v1/etimer.h
+ * @brief SPC5xx eTimer header file.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#ifndef _ETIMER_H_
+#define _ETIMER_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5 FlexPWM registers block.
+ * @note Redefined from the SPC5 headers because the non uniform
+ * declaration of the SubModules registers among the various
+ * sub-families.
+ */
+struct spc5_etimer_submodule {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP1 :16;
+ } B;
+ } COMP1; /* Compare Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP2 :16;
+ } B;
+ } COMP2; /* Compare Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT1 :16;
+ } B;
+ } CAPT1; /* Capture Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT2 :16;
+ } B;
+ } CAPT2; /* Capture Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LOAD :16;
+ } B;
+ } LOAD; /* Load Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HOLD :16;
+ } B;
+ } HOLD; /* Hold Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTR :16;
+ } B;
+ } CNTR; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTMODE :3;
+ vuint16_t PRISRC :5;
+ vuint16_t ONCE :1;
+ vuint16_t LENGTH :1;
+ vuint16_t DIR :1;
+ vuint16_t SECSRC :5;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OEN :1;
+ vuint16_t RDNT :1;
+ vuint16_t INPUT :1;
+ vuint16_t VAL :1;
+ vuint16_t FORCE :1;
+ vuint16_t COFRC :1;
+ vuint16_t COINIT :2;
+ vuint16_t SIPS :1;
+ vuint16_t PIPS :1;
+ vuint16_t OPS :1;
+ vuint16_t MSTR :1;
+ vuint16_t OUTMODE :4;
+ } B;
+ } CTRL2; /* Control Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t STPEN :1;
+ vuint16_t ROC :2;
+ vuint16_t FMODE :1;
+ vuint16_t FDIS :4;
+ vuint16_t C2FCNT :3;
+ vuint16_t C1FCNT :3;
+ vuint16_t DBGEN :2;
+ } B;
+ } CTRL3; /* Control Register 3 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :6;
+ vuint16_t WDF :1;
+ vuint16_t RCF :1;
+ vuint16_t ICF2 :1;
+ vuint16_t ICF1 :1;
+ vuint16_t IEHF :1;
+ vuint16_t IELF :1;
+ vuint16_t TOF :1;
+ vuint16_t TCF2 :1;
+ vuint16_t TCF1 :1;
+ vuint16_t TCF :1;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ICF2DE :1;
+ vuint16_t ICF1DE :1;
+ vuint16_t CMPLD2DE :1;
+ vuint16_t CMPLD1DE :1;
+ vuint16_t :2;
+ vuint16_t WDFIE :1;
+ vuint16_t RCFIE :1;
+ vuint16_t ICF2IE :1;
+ vuint16_t ICF1IE :1;
+ vuint16_t IEHFIE :1;
+ vuint16_t IELFIE :1;
+ vuint16_t TOFIE :1;
+ vuint16_t TCF2IE :1;
+ vuint16_t TCF1IE :1;
+ vuint16_t TCFIE :1;
+ } B;
+ } INTDMA; /* Interrupt and DMA Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD1 :16;
+ } B;
+ } CMPLD1; /* Compare Load Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD2 :16;
+ } B;
+ } CMPLD2; /* Compare Load Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CLC2 :3;
+ vuint16_t CLC1 :3;
+ vuint16_t CMPMODE :2;
+ vuint16_t CPT2MODE :2;
+ vuint16_t CPT1MODE :2;
+ vuint16_t CFWM :2;
+ vuint16_t ONESHOT :1;
+ vuint16_t ARM :1;
+ } B;
+ } CCCTRL; /* Compare and Capture Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FILTCNT :3;
+ vuint16_t FILTPER :8;
+ } B;
+ } FILT; /* Input Filter Register */
+
+};
+/* end of ETIMER_CHANNEL_tag */
+
+struct spc5_etimer {
+
+ struct spc5_etimer_submodule CHANNEL[8];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOL :16;
+ } B;
+ } WDTOL; /* Watchdog Time-out Low Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOH :16;
+ } B;
+ } WDTOH; /* Watchdog Time-out High Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t FTEST :1;
+ vuint16_t FIE :4;
+ vuint16_t :4;
+ vuint16_t FLVL :4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t FFPIN :4;
+ vuint16_t :4;
+ vuint16_t FFLAG :4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FFILTCNT :3;
+ vuint16_t FFILTPER :8;
+ } B;
+ } FFILT; /* Fault Filter Register */
+
+ int16_t ETIMER_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t ENBL :8;
+ } B;
+ } ENBL; /* Channel Enable Register */
+
+ int16_t ETIMER_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :11;
+ vuint16_t DREQ :5;
+ } B;
+ } DREQ[4]; /* DMA Request 0->3 Select Register */
+
+};
+/* end of ETIMER_tag */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name FlexPWM units references
+ * @{
+ */
+#if SPC5_HAS_ETIMER0
+#define SPC5_ETIMER_0 (*(volatile struct spc5_etimer *)0xFFE18000UL)
+#endif
+
+#if SPC5_HAS_ETIMER1
+#define SPC5_ETIMER_1 (*(volatile struct spc5_etimer *)0xFFE1C000UL)
+#endif
+
+#if SPC5_HAS_ETIMER2
+#define SPC5_ETIMER_2 (*(volatile struct spc5_etimer *)0xFFE20000UL)
+#endif
+/** @} */
+
+#endif /* _FLEXPWM_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
index a2bd437e0..c90ef85e9 100644
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
+++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
@@ -740,126 +740,126 @@ void icu_lld_init(void) {
#if SPC5_ICU_USE_SMOD0
/* Driver initialization.*/
icuObjectInit(&ICUD1);
- ICUD1.etimerp = &ETIMER_0;
+ ICUD1.etimerp = &SPC5_ETIMER_0;
ICUD1.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD1
/* Driver initialization.*/
icuObjectInit(&ICUD2);
- ICUD2.etimerp = &ETIMER_0;
+ ICUD2.etimerp = &SPC5_ETIMER_0;
ICUD2.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD2
/* Driver initialization.*/
icuObjectInit(&ICUD3);
- ICUD3.etimerp = &ETIMER_0;
+ ICUD3.etimerp = &SPC5_ETIMER_0;
ICUD3.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD3
/* Driver initialization.*/
icuObjectInit(&ICUD4);
- ICUD4.etimerp = &ETIMER_0;
+ ICUD4.etimerp = &SPC5_ETIMER_0;
ICUD4.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD4
/* Driver initialization.*/
icuObjectInit(&ICUD5);
- ICUD5.etimerp = &ETIMER_0;
+ ICUD5.etimerp = &SPC5_ETIMER_0;
ICUD5.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD5
/* Driver initialization.*/
icuObjectInit(&ICUD6);
- ICUD6.etimerp = &ETIMER_0;
+ ICUD6.etimerp = &SPC5_ETIMER_0;
ICUD6.smod_number = 5;
#endif
#if SPC5_ICU_USE_SMOD6
/* Driver initialization.*/
icuObjectInit(&ICUD7);
- ICUD7.etimerp = &ETIMER_1;
+ ICUD7.etimerp = &SPC5_ETIMER_1;
ICUD7.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD7
/* Driver initialization.*/
icuObjectInit(&ICUD8);
- ICUD8.etimerp = &ETIMER_1;
+ ICUD8.etimerp = &SPC5_ETIMER_1;
ICUD8.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD8
/* Driver initialization.*/
icuObjectInit(&ICUD9);
- ICUD9.etimerp = &ETIMER_1;
+ ICUD9.etimerp = &SPC5_ETIMER_1;
ICUD9.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD9
/* Driver initialization.*/
icuObjectInit(&ICUD10);
- ICUD10.etimerp = &ETIMER_1;
+ ICUD10.etimerp = &SPC5_ETIMER_1;
ICUD10.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD10
/* Driver initialization.*/
icuObjectInit(&ICUD11);
- ICUD11.etimerp = &ETIMER_1;
+ ICUD11.etimerp = &SPC5_ETIMER_1;
ICUD11.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD11
/* Driver initialization.*/
icuObjectInit(&ICUD12);
- ICUD12.etimerp = &ETIMER_1;
+ ICUD12.etimerp = &SPC5_ETIMER_1;
ICUD12.smod_number = 5;
#endif
#if SPC5_ICU_USE_SMOD12
/* Driver initialization.*/
icuObjectInit(&ICUD13);
- ICUD13.etimerp = &ETIMER_2;
+ ICUD13.etimerp = &SPC5_ETIMER_2;
ICUD13.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD13
/* Driver initialization.*/
icuObjectInit(&ICUD14);
- ICUD14.etimerp = &ETIMER_2;
+ ICUD14.etimerp = &SPC5_ETIMER_2;
ICUD14.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD14
/* Driver initialization.*/
icuObjectInit(&ICUD15);
- ICUD15.etimerp = &ETIMER_2;
+ ICUD15.etimerp = &SPC5_ETIMER_2;
ICUD15.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD15
/* Driver initialization.*/
icuObjectInit(&ICUD16);
- ICUD16.etimerp = &ETIMER_2;
+ ICUD16.etimerp = &SPC5_ETIMER_2;
ICUD16.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD16
/* Driver initialization.*/
icuObjectInit(&ICUD17);
- ICUD17.etimerp = &ETIMER_2;
+ ICUD17.etimerp = &SPC5_ETIMER_2;
ICUD17.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD17
/* Driver initialization.*/
icuObjectInit(&ICUD18);
- ICUD18.etimerp = &ETIMER_2;
+ ICUD18.etimerp = &SPC5_ETIMER_2;
ICUD18.smod_number = 5;
#endif
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
index 041eb95e9..606c91d2b 100644
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
+++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
@@ -475,6 +475,7 @@
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
+#include "etimer.h"
/**
* @brief ICU driver mode.
@@ -571,7 +572,7 @@ struct ICUDriver {
/**
* @brief Pointer to the eTimerx registers block.
*/
- volatile struct ETIMER_tag *etimerp;
+ volatile struct spc5_etimer *etimerp;
/**
* @brief CCR register used for width capture.
*/
diff --git a/testhal/SPC56ELxx/PWM-ICU/Makefile b/testhal/SPC56ELxx/PWM-ICU/Makefile
new file mode 100644
index 000000000..f92194c5c
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/Makefile
@@ -0,0 +1,162 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+ USE_VLE = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/GENERIC_SPC56EL/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld
+
+# C sources here.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/evtimer.c \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/various/chprintf.c \
+ main.c
+
+# C++ sources here.
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
+MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+#TRGT = powerpc-eabi-
+TRGT = ppc-vle-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk
diff --git a/testhal/SPC56ELxx/PWM-ICU/chconf.h b/testhal/SPC56ELxx/PWM-ICU/chconf.h
new file mode 100644
index 000000000..8800269d4
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/chconf.h
@@ -0,0 +1,529 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC56ELxx/PWM-ICU/halconf.h b/testhal/SPC56ELxx/PWM-ICU/halconf.h
new file mode 100644
index 000000000..cea40f37a
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/halconf.h
@@ -0,0 +1,371 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @name Drivers enable switches
+ */
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM FALSE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU TRUE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name ADC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name CAN driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name I2C driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MAC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MMC_SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SDC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 1
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL_USB driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 64
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC56ELxx/PWM-ICU/main.c b/testhal/SPC56ELxx/PWM-ICU/main.c
new file mode 100644
index 000000000..ba6b1ad7f
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/main.c
@@ -0,0 +1,142 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Inclusion of the main header files of all the imported components in the
+ order specified in the application wizard. The file is generated
+ automatically.*/
+#include "components.h"
+
+#include "shellcmd.h"
+
+static void pwmpcb(PWMDriver *pwmp) {
+
+ (void)pwmp;
+ palClearPad(PORT_D, PD_LED1);
+}
+
+static void pwmc1cb(PWMDriver *pwmp) {
+
+ (void)pwmp;
+ palSetPad(PORT_D, PD_LED1);
+}
+
+static PWMConfig pwmcfg = {
+ 250000, /* 250kHz PWM clock frequency.*/
+ 50000, /* Initial PWM period 0.2s.*/
+ pwmpcb,
+ {
+ {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb},
+ {PWM_OUTPUT_DISABLED, NULL}
+ },
+ EDGE_ALIGNED_PWM
+};
+
+icucnt_t last_width, last_period;
+
+static void icuwidthcb(ICUDriver *icup) {
+
+ palSetPad(PORT_D, PD_LED2);
+ last_width = icuGetWidth(icup);
+}
+
+static void icuperiodcb(ICUDriver *icup) {
+
+ palClearPad(PORT_D, PD_LED2);
+ last_period = icuGetPeriod(icup);
+}
+
+static ICUConfig icucfg = {
+ ICU_INPUT_ACTIVE_HIGH,
+ 250000, /* 250kHz ICU clock frequency.*/
+ icuwidthcb,
+ icuperiodcb,
+ NULL,
+ ICU_CHANNEL_1
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+ /*
+ * Initializes the PWM driver 1 and ICU driver 1.
+ * GPIOD10 is the PWM output.
+ * GPIOA0 is the ICU input.
+ * The two pins have to be externally connected together.
+ */
+ icuStart(&ICUD1, &icucfg);
+ icuEnable(&ICUD1);
+
+ /* Sets A0 alternative function.*/
+ SIU.PCR[0].R = 0b0100010100000100;
+
+ pwmStart(&PWMD1, &pwmcfg);
+ /* Sets D10 alternative function.*/
+ SIU.PCR[58].R = 0b0100010100000100;
+
+ chThdSleepMilliseconds(2000);
+
+ /*
+ * Starts the PWM channel 0 using 75% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes the PWM channel 0 to 50% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes the PWM channel 0 to 25% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes PWM period and the PWM channel 0 to 50% duty cycle.
+ */
+ pwmChangePeriod(&PWMD1, 25000);
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Disables channel 0 and stops the drivers.
+ */
+ pwmDisableChannel(&PWMD1, 0);
+ pwmStop(&PWMD1);
+ icuDisable(&ICUD1);
+ icuStop(&ICUD1);
+ palClearPad(PORT_D, PD_LED3);
+ palClearPad(PORT_D, PD_LED4);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
diff --git a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h
new file mode 100644
index 000000000..9ed832887
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h
@@ -0,0 +1,219 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * SPC56ELxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ */
+
+#define SPC56ELxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT FALSE
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_DISABLE_WATCHDOG TRUE
+#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
+#define SPC5_FMPLL0_IDF_VALUE 5
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC
+#define SPC5_FMPLL1_IDF_VALUE 5
+#define SPC5_FMPLL1_NDIV_VALUE 60
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_SYSCLK_DIVIDER_VALUE 2
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0
+#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#define SPC5_SWG_DIVIDER_VALUE 2
+#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
+#define SPC5_FLEXRAY_DIVIDER_VALUE 2
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
+#define SPC5_FLEXCAN_DIVIDER_VALUE 2
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 TRUE
+#define SPC5_SERIAL_USE_LINFLEX1 TRUE
+#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * PWM driver system settings.
+ */
+#define SPC5_PWM_USE_FLEXPWM0 TRUE
+#define SPC5_PWM_USE_SMOD0 TRUE
+#define SPC5_PWM_USE_SMOD1 FALSE
+#define SPC5_PWM_USE_SMOD2 FALSE
+#define SPC5_PWM_USE_SMOD3 FALSE
+#define SPC5_PWM_SMOD0_PRIORITY 7
+#define SPC5_PWM_SMOD1_PRIORITY 7
+#define SPC5_PWM_SMOD2_PRIORITY 7
+#define SPC5_PWM_SMOD3_PRIORITY 7
+#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_PWM_USE_FLEXPWM1 TRUE
+#define SPC5_PWM_USE_SMOD4 TRUE
+#define SPC5_PWM_USE_SMOD5 FALSE
+#define SPC5_PWM_USE_SMOD6 FALSE
+#define SPC5_PWM_USE_SMOD7 FALSE
+#define SPC5_PWM_SMOD4_PRIORITY 7
+#define SPC5_PWM_SMOD5_PRIORITY 7
+#define SPC5_PWM_SMOD6_PRIORITY 7
+#define SPC5_PWM_SMOD7_PRIORITY 7
+#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_ETIMER0 TRUE
+#define SPC5_ICU_USE_SMOD0 TRUE
+#define SPC5_ICU_USE_SMOD1 FALSE
+#define SPC5_ICU_USE_SMOD2 FALSE
+#define SPC5_ICU_USE_SMOD3 FALSE
+#define SPC5_ICU_USE_SMOD4 FALSE
+#define SPC5_ICU_USE_SMOD5 FALSE
+#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_ETIMER1 FALSE
+#define SPC5_ICU_USE_SMOD6 FALSE
+#define SPC5_ICU_USE_SMOD7 FALSE
+#define SPC5_ICU_USE_SMOD8 FALSE
+#define SPC5_ICU_USE_SMOD9 FALSE
+#define SPC5_ICU_USE_SMOD10 FALSE
+#define SPC5_ICU_USE_SMOD11 FALSE
+#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_ETIMER2 FALSE
+#define SPC5_ICU_USE_SMOD12 FALSE
+#define SPC5_ICU_USE_SMOD13 FALSE
+#define SPC5_ICU_USE_SMOD14 FALSE
+#define SPC5_ICU_USE_SMOD15 FALSE
+#define SPC5_ICU_USE_SMOD16 FALSE
+#define SPC5_ICU_USE_SMOD17 FALSE
+#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/testhal/SPC56ELxx/PWM-ICU/readme.txt b/testhal/SPC56ELxx/PWM-ICU/readme.txt
new file mode 100644
index 000000000..b17dba82f
--- /dev/null
+++ b/testhal/SPC56ELxx/PWM-ICU/readme.txt
@@ -0,0 +1,27 @@
+*****************************************************************************
+** ChibiOS/RT HAL - PWM/ICU drivers demo for SPC56ELxx. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STMicroelectronics SPC56ELxx microcontroller installed on
+XPC56xx EVB Motherboard.
+
+** The Demo **
+
+The application demonstrates the use of the SPC56ELxx PWM-ICU drivers.
+
+** Board Setup **
+
+- Connect D10 and A0 together.
+
+** Build Procedure **
+
+The demo has been tested using HighTec compiler.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+
+ http://www.st.com