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Add CAN driver for LPC17xx. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6743 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
theshed 2014-03-01 21:31:11 +00:00
parent 3356d32039
commit 4353bdce7e
15 changed files with 3931 additions and 2 deletions
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12
boards/EA_LPCXPRESSO_LPC1769/board.c
View File

@ -32,6 +32,7 @@ const PALConfig pal_default_config = {
};
#endif
#if HAL_USE_MAC
/*
* Board Ethernet pins configuration.
* ENET_REF_CLK pin must be set before macInit().
@ -51,6 +52,7 @@ static void board_eth_pin_config(void) {
LPC_PINCON->PINMODE3 |= (2UL << 2) | (2UL << 0); /* Disable pull-up on ENET_MDIO P1.17, ENET_MDC P1.16 */
}
#endif
/*
* Early initialization code.
@ -88,4 +90,14 @@ void boardInit(void) {
/* DAC pin config */
/* DAC pin set in dac_lld_start() */
#if HAL_USE_CAN
/* CAN config i/o */
LPC_PINCON->PINSEL0 |= (1UL << 2) | (1UL << 0); /* Set CAN1 TD1 P0.1 and RD1 P0.0 pins. */
LPC_PINCON->PINMODE0 |= (2UL << 2) | (2UL << 0); /* Disable pull-up on TD1 and RD1 pins.*/
LPC_PINCON->PINSEL0 |= (2UL << 10) | (2UL << 8); /* Set CAN2 TD2 P0.5 and RD2 P0.4 pins. */
LPC_PINCON->PINMODE0 |= (2UL << 10) | (2UL << 8); /* Disable pull-up on TD1 and RD1 pins.*/
#endif
}

8
boards/EA_LPCXPRESSO_LPC1769/board.h
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@ -35,6 +35,10 @@
#define BOARD_PHY_RMII
//#define BOARD_PHY_ADDRESS
#define LPC17xx_HAS_CAN1 TRUE
#define LPC17xx_HAS_CAN2 TRUE
/*
* Board frequencies.
*/
@ -44,7 +48,8 @@
/*
* GPIO 0 initial setup.
*/
#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED2_RED)
#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED2_RED) | \
PAL_PORT_BIT(GPIO0_LED3_EXT)
#define VAL_GPIO0DATA 0x00000000
/*
@ -75,6 +80,7 @@
* Pin definitions.
*/
#define GPIO0_LED2_RED 22
#define GPIO0_LED3_EXT 28 /* Connect LED to board. */
#define GPIO2_PIN12_TO_GND 12

657
os/hal/platforms/LPC17xx/can_lld.c Normal file
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@ -0,0 +1,657 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file LPC17xx/can_lld.c
* @brief LPC17xx CAN subsystem low level driver source.
*
* @addtogroup CAN
* @{
*/
/*
This file has been contributed by:
Marcin Jokel.
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_CAN || defined(__DOXYGEN__)
/* TODO: FullCAN mode. */
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief CAN1 driver identifier.*/
#if LPC17xx_CAN_USE_CAN1 || defined(__DOXYGEN__)
CANDriver CAND1;
#endif
/** @brief CAN2 driver identifier.*/
#if LPC17xx_CAN_USE_CAN2 || defined(__DOXYGEN__)
CANDriver CAND2;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#if LPC17xx_CAN_USE_FILTER
/**
* @brief Copy table to filter ram.
*
* @param[in] reg
* @param[in] ptable
* @param[in] addr_start
* @param[in] addr_end
*
* @notapi
*/
static void can_lld_copy_table_to_ram(volatile uint32_t * reg,
const uint32_t * ptable,
uint32_t addr_start,
uint32_t addr_end) {
uint32_t i;
if (reg != NULL) {
*reg = ((addr_start * 4) << 2);
}
for (i = addr_start; i < addr_end; i++) {
LPC_CANAF_RAM->mask[i] = ptable[i];
}
}
/**
* @brief Programs the filters.
*
* @param[in] cfc pointer to the can filter configuration structure
*
* @notapi
*/
static void can_lld_set_filter( const CANFilterConfig *cfc) {
uint32_t addr_start;
uint32_t addr_end;
LPC_CANAF->AFMR = AFMR_ACC_OFF; /* Acceptance filter off mode. */
addr_start = cfc->fc_id_table_n;
if (addr_start > 0) {
can_lld_copy_table_to_ram(NULL, cfc->fc_id_table, 0, addr_start);
}
addr_start = cfc->fc_id_table_n;
addr_end = cfc->std_id_table_n;
can_lld_copy_table_to_ram(&LPC_CANAF->SFF_sa, cfc->std_id_table, addr_start, addr_end);
addr_start = addr_end;
addr_end += cfc->std_range_id_table_n;
can_lld_copy_table_to_ram(&LPC_CANAF->SFF_GRP_sa, cfc->std_range_id_table, addr_start, addr_end);
addr_start = addr_end;
addr_end += cfc->ext_id_table_n;
can_lld_copy_table_to_ram(&LPC_CANAF->EFF_sa, cfc->ext_id_table, addr_start, addr_end);
addr_start = addr_end;
addr_end += cfc->ext_range_id_table_n;
can_lld_copy_table_to_ram(&LPC_CANAF->EFF_GRP_sa, cfc->ext_range_id_table, addr_start, addr_end);
LPC_CANAF->ENDofTable = (addr_end * 4) << 2;
LPC_CANAF->AFMR = cfc->afmr;
}
#endif
/**
* @brief Common TX ISR handler.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
static void can_lld_tx_handler(CANDriver *canp) {
/* All transmit buffers are available.*/
if (canp->can->GSR & CANGSR_TBS) {
chSysLockFromIsr();
while (chSemGetCounterI(&canp->txsem) < 0)
chSemSignalI(&canp->txsem);
chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));
chSysUnlockFromIsr();
}
}
/**
* @brief Common RX ISR handler.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] status
* @notapi
*/
static void can_lld_rx_handler(CANDriver *canp, uint32_t status) {
/* No more receive events until the queue 0 has been emptied.*/
canp->can->IER &= ~CANIER_RIE;
chSysLockFromIsr();
while (chSemGetCounterI(&canp->rxsem) < 0)
chSemSignalI(&canp->rxsem);
chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));
chSysUnlockFromIsr();
if (( status & CANICR_DOI) > 0) {
/* Overflow events handling.*/
canp->can->CMR = CANCMR_CDO;
chSysLockFromIsr();
chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
chSysUnlockFromIsr();
}
}
/**
* @brief Error ISR handler.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] flags
*
* @notapi
*/
static void can_lld_error_handler(CANDriver *canp, uint32_t status) {
uint32_t flags;
/* Error event.*/
/* The high 16-bits of the ICR register (error codes for bus error)
is copied unchanged in the upper half word of the listener flags mask.*/
flags = status & 0xFFFF0000;
if (status & CANICR_EI)
flags |= CAN_WARNING_ERROR;
if (status & CANICR_EPI)
flags |= CAN_PASSIVE_ERROR;
if (status & CANICR_BEI)
flags |= CAN_BUS_ERROR;
chSysLockFromIsr();
chEvtBroadcastFlagsI(&canp->error_event, flags);
chSysUnlockFromIsr();
}
#if CAN_USE_SLEEP_MODE
/**
* @brief Wake up ISR handler.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
static void can_lld_wakeup_handler(CANDriver *canp) {
/* Wakeup event.*/
canp->state = CAN_READY;
can_lld_wakeup(canp);
chSysLockFromIsr();
chEvtBroadcastI(&canp->wakeup_event);
chSysUnlockFromIsr();
}
#endif /* CAN_USE_SLEEP_MODE */
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if LPC17xx_CAN_USE_CAN1 || LPC17xx_CAN_USE_CAN2 ||defined(__DOXYGEN__)
/**
* @brief CAN Common, CAN 1 Tx, CAN 1 Rx, CAN 2 Tx, CAN 2 Rx.
*
* @isr
*/
CH_IRQ_HANDLER(VectorA4) {
#if LPC17xx_CAN_USE_CAN1
volatile uint32_t can1_status;
#endif
#if LPC17xx_CAN_USE_CAN2
volatile uint32_t can2_status;
#endif
CH_IRQ_PROLOGUE();
#if LPC17xx_CAN_USE_CAN1
can1_status = LPC_CAN1->ICR;
#endif
#if LPC17xx_CAN_USE_CAN2
can2_status = LPC_CAN2->ICR;
#endif
#if LPC17xx_CAN_USE_CAN1
if (can1_status & 0x000007FF) {
if (can1_status & (CANICR_EI | CANICR_EPI | CANICR_BEI)) {
can_lld_error_handler(&CAND1, can1_status);
}
if (can1_status & (CANICR_RI | CANICR_DOI)) {
can_lld_rx_handler(&CAND1, can1_status);
}
if (can1_status & (CANICR_TI1 | CANICR_TI2 | CANICR_TI3)){
can_lld_tx_handler(&CAND1);
}
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (can2_status & 0x000007FF) {
if (can2_status & CANICR_EI) {
can_lld_error_handler(&CAND2, can2_status);
}
if (can2_status & (CANICR_RI | CANICR_DOI)) {
can_lld_rx_handler(&CAND2, can2_status);
}
if (can2_status & (CANICR_TI1 | CANICR_TI2 | CANICR_TI3)){
can_lld_tx_handler(&CAND2);
}
}
#endif
CH_IRQ_EPILOGUE();
}
#if CAN_USE_SLEEP_MODE
/**
* @brief CAN Common, CAN 1 Tx, CAN 1 Rx, CAN 2 Tx, CAN 2 Rx.
*
* @isr
*/
CH_IRQ_HANDLER(VectorC8) {
#if LPC17xx_CAN_USE_CAN1
uint32_t can1_status;
#endif
#if LPC17xx_CAN_USE_CAN2
uint32_t can2_status;
#endif
CH_IRQ_PROLOGUE();
#if LPC17xx_CAN_USE_CAN1
can1_status = LPC_CAN1->ICR;
#endif
#if LPC17xx_CAN_USE_CAN2
can2_status = LPC_CAN2->ICR;
#endif
#if LPC17xx_CAN_USE_CAN1
if (can1_status & CANICR_WUI) {
can_lld_wakeup_handler(&CAND1);
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (can2_status & CANICR_WUI) {
can_lld_wakeup_handler(&CAND2);
}
#endif
CH_IRQ_EPILOGUE();
}
#endif /* CAN_USE_SLEEP_MODE */
#endif /* LPC17xx_CAN_USE_CAN1 || LPC17xx_CAN_USE_CAN2 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level CAN driver initialization.
*
* @notapi
*/
void can_lld_init(void) {
#if LPC17xx_CAN_USE_CAN1
/* Driver initialization.*/
canObjectInit(&CAND1);
CAND1.can = LPC_CAN1;
#endif
#if LPC17xx_CAN_USE_CAN2
/* Driver initialization.*/
canObjectInit(&CAND2);
CAND2.can = LPC_CAN2;
#endif
}
/**
* @brief Configures and activates the CAN peripheral.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
void can_lld_start(CANDriver *canp) {
#if LPC17xx_CAN_USE_CAN1
if (&CAND1 == canp) {
LPC_SC->PCONP |= (1UL << 13);
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (&CAND2 == canp) {
LPC_SC->PCONP |= (1UL << 14);
}
#endif
canp->can->MOD = CANMOD_RM; /* Reset mode. */
#if !LPC17xx_CAN_USE_FILTER
LPC_CANAF->AFMR = AFMR_ACC_BP; /* Bypass can filter. */
#endif
/* Entering initialization mode. */
canp->state = CAN_STARTING;
canp->can->BTR = canp->config->btr; /* BTR initialization.*/
canp->can->CMR = CANCMR_RRB;
/* Interrupt sources initialization.*/
canp->can->IER = CANIER_TIE3 | CANIER_TIE2 | CANIER_BEIE |
CANIER_EPIE | CANIER_DOIE | CANIER_EIE |
CANIER_TIE1 | CANIER_RIE;
#if CAN_USE_SLEEP_MODE
canp->can->IER |= CANIER_WUIE;
nvicEnableVector(CANActivity_IRQn,
CORTEX_PRIORITY_MASK(LPC17xx_CAN_IRQ_PRIORITY));
#endif /* CAN_USE_SLEEP_MODE */
canp->can->MOD = canp->config->mod; /* Operating mode. */
nvicEnableVector(CAN_IRQn,
CORTEX_PRIORITY_MASK(LPC17xx_CAN_IRQ_PRIORITY));
}
/**
* @brief Deactivates the CAN peripheral.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
void can_lld_stop(CANDriver *canp) {
/* If in ready state then disables the CAN peripheral.*/
if (canp->state == CAN_READY) {
canp->can->MOD = CANMOD_RM; /* Reset mode. */
canp->can->IER = 0;
#if (LPC17xx_CAN_USE_CAN1 && LPC17xx_CAN_USE_CAN2) == 0
nvicDisableVector(CAN_IRQn); /* Interrupt disabled only if one CAN is in use. */
#endif
#if LPC17xx_CAN_USE_CAN1
if (&CAND1 == canp) {
LPC_SC->PCONP &= ~(1UL << 13);
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (&CAND2 == canp) {
LPC_SC->PCONP &= ~(1UL << 14);
}
#endif
#if CAN_USE_SLEEP_MODE
nvicDisableVector(CANActivity_IRQn);
#endif /* CAN_USE_SLEEP_MODE */
}
}
/**
* @brief Determines whether a frame can be transmitted.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
*
* @return The queue space availability.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
*
* @notapi
*/
bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
switch (mailbox) {
case CAN_ANY_MAILBOX:
return ((canp->can->SR & (CANSR_TBS1 | CANSR_TBS2 | CANSR_TBS3)) != 0);
case 1:
return (canp->can->SR & CANSR_TBS1) != 0;
case 2:
return (canp->can->SR & CANSR_TBS2) != 0;
case 3:
return (canp->can->SR & CANSR_TBS3) != 0;
default:
return FALSE;
}
}
/**
* @brief Inserts a frame into the transmit queue.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] ctfp pointer to the CAN frame to be transmitted
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
*
* @notapi
*/
void can_lld_transmit(CANDriver *canp,
canmbx_t mailbox,
const CANTxFrame *ctfp) {
volatile uint32_t * tfi;
uint32_t tbs_n;
uint32_t sr;
tbs_n = mailbox;
if (mailbox == CAN_ANY_MAILBOX) {
sr = canp->can->SR;
if (sr & CANSR_TBS1) {
tbs_n = 1;
}
else if (sr & CANSR_TBS2) {
tbs_n = 2;
}
else if (sr & CANSR_TBS3) {
tbs_n = 3;
}
else {
return;
}
}
/* Pointer to a free transmission mailbox.*/
switch (tbs_n) {
case 1:
tfi = &canp->can->TFI1;
break;
case 2:
tfi = &canp->can->TFI2;
break;
case 3:
tfi = &canp->can->TFI3;
break;
default:
return;
}
/* Preparing the message.*/
* tfi = ((uint32_t)ctfp->IDE << 31) | ((uint32_t)ctfp->RTR << 30) |
(((uint32_t)ctfp->DLC) << 16); /* CAN Transmit Frame Information Register. */
if (ctfp->IDE)
*(tfi + 1) = ctfp->EID; /* CAN Transmit Identifier register 29-bit. */
else
*(tfi + 1) = ctfp->SID; /* CAN Transmit Identifier register 11-bit. */
*(tfi + 2) = ctfp->data32[0]; /* CAN Transmit Data Register A. */
*(tfi + 3) = ctfp->data32[1]; /* CAN Transmit Data Register B. */
#if LPC17xx_CAN_USE_LOCAL_SELF_TEST
canp->can->CMR = (1UL << (4 + tbs_n)) | CANCMR_SRR;
#else
canp->can->CMR = (1UL << (4 + tbs_n)) | CANCMR_TR;
#endif
}
/**
* @brief Determines whether a frame has been received.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
*
* @return The queue space availability.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
*
* @notapi
*/
bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
switch (mailbox) {
case CAN_ANY_MAILBOX:
case 1:
return ((canp->can->GSR & CANGSR_RBS) != 0);
default:
return FALSE;
}
}
/**
* @brief Receives a frame from the input queue.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
* @param[out] crfp pointer to the buffer where the CAN frame is copied
*
* @notapi
*/
void can_lld_receive(CANDriver *canp,
canmbx_t mailbox,
CANRxFrame *crfp) {
uint32_t rfs, rid;
switch (mailbox) {
case CAN_ANY_MAILBOX:
case 1:
/* Fetches the message.*/
rfs = canp->can->RFS;
rid = canp->can->RID;
crfp->data32[0] = canp->can->RDA;
crfp->data32[1] = canp->can->RDB;
/* Releases the mailbox.*/
canp->can->CMR = CANCMR_RRB;
/* Re-enables the interrupt in order to generate
events again. */
canp->can->IER |= CANIER_RIE;
break;
default:
/* Should not happen, do nothing.*/
return;
}
/* Decodes the various fields in the RX frame.*/
crfp->RTR = (rfs & CANRFS_RTR) >> 30;
crfp->IDE = (rfs & CANRFS_FF) >> 31;
if (crfp->IDE) {
crfp->EID = rid;
}
else {
crfp->SID = rid;
}
crfp->DLC = (rfs & CANRFS_DLC) >> 16;
crfp->IDF = (uint16_t)(rfs & CANRFS_ID);
}
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
/**
* @brief Enters the sleep mode.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
void can_lld_sleep(CANDriver *canp) {
canp->can->MOD |= CANMOD_SM;
}
/**
* @brief Enforces leaving the sleep mode.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
void can_lld_wakeup(CANDriver *canp) {
uint32_t reg_val;
#if LPC17xx_CAN_USE_CAN1
if (&CAND1 == canp) {
reg_val = (1UL << 1);
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (&CAND2 == canp) {
reg_val = (1UL << 2);
}
#endif
LPC_SC->CANSLEEPCLR = reg_val;
canp->can->MOD &= ~CANMOD_SM;
LPC_SC->CANWAKEFLAGS = reg_val;
}
#endif /* CAN_USE_SLEEP_MODE */
#if LPC17xx_CAN_USE_FILTER
void canSetFilter(const CANFilterConfig *cfc) {
can_lld_set_filter(cfc);
}
#endif
#endif /* HAL_USE_CAN */
/** @} */

645
os/hal/platforms/LPC17xx/can_lld.h Normal file
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@ -0,0 +1,645 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file LPC17xx/can_lld.h
* @brief LPC17xx CAN subsystem low level driver header.
*
* @addtogroup CAN
* @{
*/
/*
This file has been contributed by:
Marcin Jokel.
*/
#ifndef _CAN_LLD_H_
#define _CAN_LLD_H_
#if HAL_USE_CAN || defined(__DOXYGEN__)
/* TODO: FullCAN mode. */
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* CAN Mode register bits.
*/
#define CANMOD_RM (1UL << 0)
#define CANMOD_LOM (1UL << 1)
#define CANMOD_STM (1UL << 2)
#define CANMOD_TPM (1UL << 3)
#define CANMOD_SM (1UL << 4)
#define CANMOD_RPM (1UL << 5)
#define CANMOD_TM (1UL << 7)
/*
* CAN Command register bits.
*/
#define CANCMR_TR (1UL << 0)
#define CANCMR_AT (1UL << 1)
#define CANCMR_RRB (1UL << 2)
#define CANCMR_CDO (1UL << 3)
#define CANCMR_SRR (1UL << 4)
#define CANCMR_STB1 (1UL << 5)
#define CANCMR_STB2 (1UL << 6)
#define CANCMR_STB3 (1UL << 7)
/*
* CAN Global Status register bits.
*/
#define CANGSR_RBS (1UL << 0)
#define CANGSR_DOS (1UL << 1)
#define CANGSR_TBS (1UL << 2)
#define CANGSR_TCS (1UL << 3)
#define CANGSR_RS (1UL << 4)
#define CANGSR_TS (1UL << 5)
#define CANGSR_ES (1UL << 6)
#define CANGSR_BS (1UL << 7)
#define CANGSR_RXERR 0x00FF0000
#define CANGSR_TXERR 0xFF000000
/*
* CAN Interrupt and Capture register bits.
*/
#define CANICR_RI (1UL << 0)
#define CANICR_TI1 (1UL << 1)
#define CANICR_EI (1UL << 2)
#define CANICR_DOI (1UL << 3)
#define CANICR_WUI (1UL << 4)
#define CANICR_EPI (1UL << 5)
#define CANICR_ALI (1UL << 6)
#define CANICR_BEI (1UL << 7)
#define CANICR_IDI (1UL << 8)
#define CANICR_TI2 (1UL << 9)
#define CANICR_TI3 (1UL << 10)
#define CANICR_ERRBIT 0x001F0000
#define CANICR_ERRBIT_SOF 0x00030000
#define CANICR_ERRBIT_ID28_ID21 0x00020000
#define CANICR_ERRBIT_ID20_ID18 0x00060000
#define CANICR_ERRBIT_SRTR 0x00040000
#define CANICR_ERRBIT_IDE 0x00050000
#define CANICR_ERRBIT_ID17_ID13 0x00070000
#define CANICR_ERRBIT_ID12_ID5 0x000F0000
#define CANICR_ERRBIT_ID4_ID0 0x000E0000
#define CANICR_ERRBIT_RTR 0x000C0000
#define CANICR_ERRBIT_RES_BIT1 0x000D0000
#define CANICR_ERRBIT_RES_BIT0 0x00090000
#define CANICR_ERRBIT_DATA_LEN_CODE 0x000B0000
#define CANICR_ERRBIT_DATA_FIELD 0x000A0000
#define CANICR_ERRBIT_CRC_SEQ 0x00080000
#define CANICR_ERRBIT_CRC_DEL 0x00180000
#define CANICR_ERRBIT_ACK_SLOT 0x00190000
#define CANICR_ERRBIT_ACK_DEL 0x001B0000
#define CANICR_ERRBIT_EOF 0x001A0000
#define CANICR_ERRBIT_INTERMISSION 0x00120000
#define CANICR_ERRBIT_ACTIVE_ERROR 0x00110000
#define CANICR_ERRBIT_PASSIVE_ERROR 0x00160000
#define CANICR_ERRBIT_TOL_DOM_BITS 0x00130000
#define CANICR_ERRBIT_ERROR_DEL 0x00170000
#define CANICR_ERRBIT_OVERLOAD 0x001C0000
#define CANICR_ERRDIR (1UL << 21)
#define CANICR_ERRC (3UL << 22)
#define CANICR_ERRC_BIT_ERR (0UL << 22)
#define CANICR_ERRC_FORM_ERR (1UL << 22)
#define CANICR_ERRC_STUFF_ERR (2UL << 22)
#define CANICR_ERRC_OTHER_ERR (3UL << 22)
#define CANICR_ALCBIT 0xFF000000
/*
* CAN Interrupt Enable register bits.
*/
#define CANIER_RIE (1UL << 0)
#define CANIER_TIE1 (1UL << 1)
#define CANIER_EIE (1UL << 2)
#define CANIER_DOIE (1UL << 3)
#define CANIER_WUIE (1UL << 4)
#define CANIER_EPIE (1UL << 5)
#define CANIER_ALIE (1UL << 6)
#define CANIER_BEIE (1UL << 7)
#define CANIER_IDIE (1UL << 8)
#define CANIER_TIE2 (1UL << 9)
#define CANIER_TIE3 (1UL << 10)
/*
* CAN Bus Timing register bits.
*/
#define CANBTR_BRP(t) ((t) << 0)
#define CANBTR_SJW(t) ((t) << 14)
#define CANBTR_TESG1(t) ((t) << 16)
#define CANBTR_TESG2(t) ((t) << 20)
#define CANBTR_SAM (1UL << 23)
/*
* CAN Status register bits.
*/
#define CANSR_RBS (1UL << 0)
#define CANSR_DOS (1UL << 1)
#define CANSR_TBS1 (1UL << 2)
#define CANSR_TCS1 (1UL << 3)
#define CANSR_RS (1UL << 4)
#define CANSR_TS1 (1UL << 5)
#define CANSR_ES (1UL << 6)
#define CANSR_BS (1UL << 7)
#define CANSR_TBS2 (1UL << 10)
#define CANSR_TCS2 (1UL << 11)
#define CANSR_TS2 (1UL << 13)
#define CANSR_TBS3 (1UL << 18)
#define CANSR_TCS3 (1UL << 19)
#define CANSR_TS3 (1UL << 21)
/*
* CAN Receive Frame Status register bits.
*/
#define CANRFS_ID 0x000001FF
#define CANRFS_BP (1UL << 10)
#define CANRFS_DLC 0x000F0000
#define CANRFS_RTR (1UL << 30)
#define CANRFS_FF (1UL << 31)
/*
* CAN Transmit Frame Information register bits.
*/
#define CANTFI_PRIO(p) ((p) << 0)
#define CANTFI_DLC(l) ((l) << 16)
#define CANTFI_RTR (1UL << 30)
#define CANTFI_FF (1UL << 31)
/*
* CAN Sleep Clear register bits.
*/
#define CANSLEEPCLR_CAN1SLEEP (1UL << 1)
#define CANSLEEPCLR_CAN2SLEEP (1UL << 2)
/*
* CAN Wake-up Flags register bits.
*/
#define CANWAKEFLAGS_CAN1WAKE (1UL << 1)
#define CANWAKEFLAGS_CAN2WAKE (1UL << 2)
/*
* Central Transmit Status register bits.
*/
#define CANTSR_TS1 (1UL << 0)
#define CANTSR_TS2 (1UL << 1)
#define CANTSR_TBS1 (1UL << 8)
#define CANTSR_TBS2 (1UL << 9)
#define CANTSR_TCS1 (1UL << 16)
#define CANTSR_TCS2 (1UL << 17)
/*
* Central Receive Status register bits.
*/
#define CANRSR_RS1 (1UL << 0)
#define CANRSR_RS2 (1UL << 1)
#define CANRSR_RB1 (1UL << 8)
#define CANRSR_RB2 (1UL << 9)
#define CANRSR_DOS1 (1UL << 16)
#define CANRSR_DOS2 (1UL << 17)
/*
* Central Miscellaneous Status register bits.
*/
#define CANMSR_E1 (1UL << 0)
#define CANMSR_E2 (1UL << 1)
#define CANMSR_BS1 (1UL << 8)
#define CANMSR_BS2 (1UL << 9)
/*
* Acceptance Filter Mode register bits.
*/
#define AFMR_ACC_OFF (1UL << 0)
#define AFMR_ACC_BP (1UL << 1)
#define AFMR_E_FCAN (1UL << 2)
/**
* @brief This switch defines whether the driver implementation supports
* a low power switch mode with automatic an wakeup feature.
*/
#define CAN_SUPPORTS_SLEEP TRUE
/**
* @brief This implementation supports three transmit mailboxes.
*/
#define CAN_TX_MAILBOXES 3
/**
* @brief This implementation supports two receive mailboxes.
*/
#define CAN_RX_MAILBOXES 1
/** @} */
/**
* @name CAN registers helper macros
* @{
*/
#define CAN_IDE_STD 0 /**< @brief Standard id. */
#define CAN_IDE_EXT 1 /**< @brief Extended id. */
#define CAN_RTR_DATA 0 /**< @brief Data frame. */
#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */
#undef CAN_LIMIT_WARNING
#undef CAN_LIMIT_ERROR
#undef CAN_BUS_OFF_ERROR
#undef CAN_FRAMING_ERROR
#define CAN_WARNING_ERROR 1
#define CAN_PASSIVE_ERROR 2
#define CAN_BUS_ERROR 4
/**
* @brief CAN filter fullCAN (standard identifier) type entry.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
#define CANFilterFCEntry(ctrl_i1, dis_i1, id_i1, ctrl_i2, dis_i2, id_i2) \
((((uint32_t)ctrl_i1) << 29) | (((uint32_t)dis_i1) << 28) | (((uint32_t)id_i1) << 16) | \
(((uint32_t)ctrl_i2) << 13) | (((uint32_t)dis_i2) << 12) | ((uint32_t)(id_i2)))
/**
* @brief CAN filter standard identifier type entry.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
#define CANFilterStdEntry(ctrl_i1, dis_i1, id_i1, ctrl_i2, dis_i2, id_i2) \
((((uint32_t)ctrl_i1) << 29) | (((uint32_t)dis_i1) << 28) | (((uint32_t)id_i1) << 16) | \
(((uint32_t)ctrl_i2) << 13) | (((uint32_t)dis_i2) << 12) | ((uint32_t)(id_i2)))
/**
* @brief CAN filter extended identifier range type entry.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
#define CANFilterStdRangeEntry(ctrl_low, dis_low, id_low, ctrl_high, dis_high, id_high) \
((((uint32_t)ctrl_low) << 29) | (((uint32_t)dis_low) << 28) | (((uint32_t)id_low) << 16) | \
(((uint32_t)ctrl_up) << 13) | (((uint32_t)dis_up) << 12) | ((uint32_t)(id_up)))
/**
* @brief CAN filter extended identifier type entry.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
#define CANFilterExtEntry(ctrl, id) \
((((uint32_t)ctrl) << 29) | ((uint32_t)(id)))
/**
* @brief CAN filter extended range identifier type entry.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
#define CANFilterExtRangeEntry(ctrl, id) \
((((uint32_t)ctrl) << 29) | ((uint32_t)(id)))
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for CAN1 is included.
*/
#if !defined(LPC17xx_CAN_USE_CAN1) || defined(__DOXYGEN__)
#define LPC17xx_CAN_USE_CAN1 FALSE
#endif
/**
* @brief CAN2 driver enable switch.
* @details If set to @p TRUE the support for CAN2 is included.
*/
#if !defined(LPC17xx_CAN_USE_CAN2) || defined(__DOXYGEN__)
#define LPC17xx_CAN_USE_CAN2 FALSE
#endif
/**
* @brief CAN1 and CAN2 interrupt priority level setting.
*/
#if !defined(LPC17xx_CAN_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define LPC17xx_CAN_IRQ_PRIORITY 11
#endif
/** @} */
/**
* @brief CAN1 and CAN2 local self test enable.
*/
#if !defined(LPC17xx_CAN_USE_LOCAL_SELF_TEST) || defined(__DOXYGEN__)
#define LPC17xx_CAN_USE_LOCAL_SELF_TEST FALSE
#endif
/** @} */
/**
* @brief CAN1 and CAN2 acceptance filter enable.
*/
#if !defined(LPC17xx_CAN_USE_FILTER) || defined(__DOXYGEN__)
#define LPC17xx_CAN_USE_FILTER FALSE
#endif
/** @} */
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if LPC17xx_CAN_USE_CAN1 && !LPC17xx_HAS_CAN1
#error "CAN1 not present in the selected device"
#endif
#if LPC17xx_CAN_USE_CAN2 && !LPC17xx_HAS_CAN2
#error "CAN2 not present in the selected device"
#endif
#if !LPC17xx_CAN_USE_CAN1 && !LPC17xx_CAN_USE_CAN2
#error "CAN driver activated but no CAN peripheral assigned"
#endif
#if !LPC17xx_CAN_USE_CAN1 && LPC17xx_CAN_USE_CAN2
#error "CAN2 requires CAN1, it cannot operate independently"
#endif
#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
#error "CAN sleep mode not supported in this architecture"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a transmission mailbox index.
*/
typedef uint32_t canmbx_t;
/**
* @brief CAN transmission frame.
* @note Accessing the frame data as word16 or word32 is not portable because
* machine data endianness, it can be still useful for a quick filling.
*/
typedef struct {
struct {
uint8_t DLC:4; /**< @brief Data length. */
uint8_t RTR:1; /**< @brief Frame type. */
uint8_t IDE:1; /**< @brief Identifier type. */
};
union {
struct {
uint32_t SID:11; /**< @brief Standard identifier.*/
};
struct {
uint32_t EID:29; /**< @brief Extended identifier.*/
};
};
union {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
uint32_t data32[2]; /**< @brief Frame data. */
};
} CANTxFrame;
/**
* @brief CAN received frame.
* @note Accessing the frame data as word16 or word32 is not portable because
* machine data endianness, it can be still useful for a quick filling.
*/
typedef struct {
struct {
uint16_t IDF:10; /**< @brief Filter id. */
};
struct {
uint8_t DLC:4; /**< @brief Data length. */
uint8_t RTR:1; /**< @brief Frame type. */
uint8_t IDE:1; /**< @brief Identifier type. */
};
union {
struct {
uint32_t SID:11; /**< @brief Standard identifier.*/
};
struct {
uint32_t EID:29; /**< @brief Extended identifier.*/
};
};
union {
uint8_t data8[8]; /**< @brief Frame data. */
uint16_t data16[4]; /**< @brief Frame data. */
uint32_t data32[2]; /**< @brief Frame data. */
};
} CANRxFrame;
/**
* @brief CAN filter standard identifier type.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
typedef const uint32_t CANFilterStd;
/**
* @brief CAN filter standard identifier range type.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
typedef const uint32_t CANFilterStdRange;
/**
* @brief CAN filter extended identifier range type.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
typedef const uint32_t CANFilterExt;
/**
* @brief CAN filter extended range identifier type.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
typedef const uint32_t CANFilterExtRange;
/**
* @brief CAN filter configuration structure.
* @note Refer to the LPC17xx reference manual for info about filters.
*/
typedef struct {
/**
* @brief Acceptance filter mode register.
*/
uint32_t afmr;
/**
* @brief FullCAN (standard identifier) table.
*/
CANFilterStd *fc_id_table;
/**
* @brief Number of positions in fullCAN (standard identifier) table.
*/
uint32_t fc_id_table_n;
/**
* @brief Standard identifier table.
*/
CANFilterStd *std_id_table;
/**
* @brief Number of positions in standard identifier table.
*/
uint32_t std_id_table_n;
/**
* @brief Standard range identifier table.
*/
CANFilterStdRange *std_range_id_table;
/**
* @brief Number of positions in standard range identifier table.
*/
uint32_t std_range_id_table_n;
/**
* @brief Extended identifier table.
*/
CANFilterExt *ext_id_table;
/**
* @brief Number of positions in extended identifier table.
*/
uint32_t ext_id_table_n;
/**
* @brief Extended range identifier table.
*/
CANFilterExtRange *ext_range_id_table;
/**
* @brief Number of positions in extended range identifier table.
*/
uint32_t ext_range_id_table_n;
} CANFilterConfig;
/**
* @brief Driver configuration structure.
*/
typedef struct {
/**
* @brief CAN MOD register initialization data.
* @note Some bits in this register are enforced by the driver regardless
* their status in this field.
*/
uint32_t mod;
/**
* @brief CAN BTR register initialization data.
* @note Some bits in this register are enforced by the driver regardless
* their status in this field.
*/
uint32_t btr;
} CANConfig;
/**
* @brief Structure representing an CAN driver.
*/
typedef struct {
/**
* @brief Driver state.
*/
canstate_t state;
/**
* @brief Current configuration data.
*/
const CANConfig *config;
/**
* @brief Transmission queue semaphore.
*/
Semaphore txsem;
/**
* @brief Receive queue semaphore.
*/
Semaphore rxsem;
/**
* @brief One or more frames become available.
* @note After broadcasting this event it will not be broadcasted again
* until the received frames queue has been completely emptied. It
* is <b>not</b> broadcasted for each received frame. It is
* responsibility of the application to empty the queue by
* repeatedly invoking @p chReceive() when listening to this event.
* This behavior minimizes the interrupt served by the system
* because CAN traffic.
* @note The flags associated to the listeners will indicate which
* receive mailboxes become non-empty.
*/
EventSource rxfull_event;
/**
* @brief One or more transmission mailbox become available.
* @note The flags associated to the listeners will indicate which
* transmit mailboxes become empty.
*
*/
EventSource txempty_event;
/**
* @brief A CAN bus error happened.
* @note The flags associated to the listeners will indicate the
* error(s) that have occurred.
*/
EventSource error_event;
#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
/**
* @brief Entering sleep state event.
*/
EventSource sleep_event;
/**
* @brief Exiting sleep state event.
*/
EventSource wakeup_event;
#endif /* CAN_USE_SLEEP_MODE */
/* End of the mandatory fields.*/
/**
* @brief Pointer to the CAN registers.
*/
LPC_CAN_TypeDef *can;
} CANDriver;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if LPC17xx_CAN_USE_CAN1 && !defined(__DOXYGEN__)
extern CANDriver CAND1;
#endif
#if LPC17xx_CAN_USE_CAN2 && !defined(__DOXYGEN__)
extern CANDriver CAND2;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void can_lld_init(void);
void can_lld_start(CANDriver *canp);
void can_lld_stop(CANDriver *canp);
bool_t can_lld_is_tx_empty(CANDriver *canp,
canmbx_t mailbox);
void can_lld_transmit(CANDriver *canp,
canmbx_t mailbox,
const CANTxFrame *crfp);
bool_t can_lld_is_rx_nonempty(CANDriver *canp,
canmbx_t mailbox);
void can_lld_receive(CANDriver *canp,
canmbx_t mailbox,
CANRxFrame *ctfp);
#if CAN_USE_SLEEP_MODE
void can_lld_sleep(CANDriver *canp);
void can_lld_wakeup(CANDriver *canp);
#endif /* CAN_USE_SLEEP_MODE */
#if LPC17xx_CAN_USE_FILTER
void canSetFilter(const CANFilterConfig *cfc);
#endif /* LPC17xx_CAN_USE_FILTER */
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_CAN */
#endif /* _CAN_LLD_H_ */
/** @} */

3
os/hal/platforms/LPC17xx/platform.mk
View File

@ -9,7 +9,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC17xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/LPC17xx/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/LPC17xx/spi_lld.c \
${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c \
${CHIBIOS}/os/hal/platforms/LPC17xx/mac_lld.c
${CHIBIOS}/os/hal/platforms/LPC17xx/mac_lld.c \
${CHIBIOS}/os/hal/platforms/LPC17xx/can_lld.c
# Required include directories

195
testhal/LPC17xx/CAN/Makefile Normal file
View File

@ -0,0 +1,195 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/boards/EA_LPCXPRESSO_LPC1769/board.mk
include $(CHIBIOS)/os/hal/platforms/LPC17xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC17xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/LPC1769.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m3
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS = -DLPC17XX -D__NEWLIB__
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

531
testhal/LPC17xx/CAN/chconf.h Normal file
View File

@ -0,0 +1,531 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN TRUE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
struct can_instance {
CANDriver *canp;
uint32_t led;
};
static const struct can_instance can1 = {&CAND1, GPIO0_LED2_RED};
static const struct can_instance can2 = {&CAND2, GPIO0_LED3_EXT}; /* Connect LED to board. */
#if LPC17xx_CAN_USE_FILTER
static const CANFilterExt cfe_id_table[2] = {
CANFilterExtEntry(0, 0x0ABCDEF0),
CANFilterExtEntry(1, 0x01234567)
};
static const CANFilterConfig canfcfg = {
0,
NULL,
0,
NULL,
0,
NULL,
0,
cfe_id_table,
2,
NULL,
0
};
#endif
/*
* Operating mode
*/
static const CANConfig cancfg = {
0,
CANBTR_SJW(0) | CANBTR_TESG2(1) |
CANBTR_TESG1(8) | CANBTR_BRP(20)
};
/*
* Receiver thread.
*/
static WORKING_AREA(can_rx1_wa, 256);
static WORKING_AREA(can_rx2_wa, 256);
static msg_t can_rx(void *p) {
struct can_instance *cip = p;
EventListener el;
CANRxFrame rxmsg;
(void)p;
chRegSetThreadName("receiver");
chEvtRegister(&cip->canp->rxfull_event, &el, 0);
while(!chThdShouldTerminate()) {
if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0)
continue;
while (canReceive(cip->canp, CAN_ANY_MAILBOX,
&rxmsg, TIME_IMMEDIATE) == RDY_OK) {
/* Process message.*/
palTogglePad(GPIO0, cip->led);
}
}
chEvtUnregister(&CAND1.rxfull_event, &el);
return 0;
}
/*
* Transmitter thread.
*/
static WORKING_AREA(can_tx_wa, 256);
static msg_t can_tx(void * p) {
CANTxFrame txmsg_can1;
CANTxFrame txmsg_can2;
(void)p;
chRegSetThreadName("transmitter");
txmsg_can1.IDE = CAN_IDE_EXT;
txmsg_can1.EID = 0x01234567;
txmsg_can1.RTR = CAN_RTR_DATA;
txmsg_can1.DLC = 8;
txmsg_can1.data32[0] = 0x55AA55AA;
txmsg_can1.data32[1] = 0x00FF00FF;
txmsg_can2.IDE = CAN_IDE_EXT;
txmsg_can2.EID = 0x0ABCDEF0;
txmsg_can2.RTR = CAN_RTR_DATA;
txmsg_can2.DLC = 8;
txmsg_can2.data32[0] = 0x66AA66AA;
txmsg_can2.data32[1] = 0x44FF44FF;
while (!chThdShouldTerminate()) {
canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg_can1, MS2ST(100));
canTransmit(&CAND2, CAN_ANY_MAILBOX, &txmsg_can2, MS2ST(100));
chThdSleepMilliseconds(500);
}
return 0;
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the CAN drivers 1 and 2.
*/
canStart(&CAND1, &cancfg);
canStart(&CAND2, &cancfg);
#if LPC17xx_CAN_USE_FILTER
canSetFilter(&canfcfg);
#endif
/*
* Starting the transmitter and receiver threads.
*/
chThdCreateStatic(can_rx1_wa, sizeof(can_rx1_wa), NORMALPRIO + 7,
can_rx, (void *)&can1);
chThdCreateStatic(can_rx2_wa, sizeof(can_rx2_wa), NORMALPRIO + 7,
can_rx, (void *)&can2);
chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7,
can_tx, NULL);
/*
* Normal main() thread activity, in this demo it does nothing.
*/
while (TRUE) {
chThdSleepMilliseconds(500);
}
return 0;
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* LPC17xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*
* IRQ priorities:
* 7...0 Lowest...highest.
*/
/*
* HAL driver system settings.
*/
#define LPC17xx_MAINOSC_ENABLE TRUE
#define LPC17xx_SYSCLK_SELECT CLKSRCSEL_MAINOSC
#define LPC17xx_MAINPLL_ENABLE TRUE
#define LPC17xx_MAINPLL_MUL 30
#define LPC17xx_MAINPLL_PREDIV 1
#define LPC17xx_USBPLL_ENABLE FALSE
#define LPC17xx_USBPLL_MUL 4
#define LPC17xx_USBPLL_DIV 4
#define LPC17xx_CCLK_DIV 3
#define LPC17xx_PCLK_SELECT PCLKSEL_CCLK
#define LPC17xx_CLKOUT_ENABLE FALSE
#define LPC17xx_CLKOUT_DIV 4
#define LPC17xx_CLKOUT_SELECT CLKOUTSEL_CCLK
/*
* GPT driver system settings.
*/
#define LPC17xx_GPT_USE_TIM0 TRUE
#define LPC17xx_GPT_USE_TIM1 TRUE
#define LPC17xx_GPT_USE_TIM2 TRUE
#define LPC17xx_GPT_USE_TIM3 TRUE
#define LPC17xx_GPT_TIM0_IRQ_PRIORITY 2
#define LPC17xx_GPT_TIM1_IRQ_PRIORITY 6
#define LPC17xx_GPT_TIM2_IRQ_PRIORITY 2
#define LPC17xx_GPT_TIM3_IRQ_PRIORITY 2
/*
* SERIAL driver system settings.
*/
#define LPC17xx_SERIAL_USE_UART0 TRUE
#define LPC17xx_SERIAL_USE_UART1 FALSE
#define LPC17xx_SERIAL_USE_UART2 FALSE
#define LPC17xx_SERIAL_USE_UART3 FALSE
#define LPC17xx_SERIAL_FIFO_PRELOAD 16
#define LPC17xx_SERIAL_UART0_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART1_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART2_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART3_IRQ_PRIORITY 3
/*
* I2C driver system settings.
*/
#define LPC17xx_I2C_USE_I2C0 FALSE
#define LPC17xx_I2C_USE_I2C1 TRUE
#define LPC17xx_I2C_USE_I2C2 FALSE
#define LPC17xx_I2C_I2C0_IRQ_PRIORITY 3
#define LPC17xx_I2C_I2C1_IRQ_PRIORITY 3
#define LPC17xx_I2C_I2C2_IRQ_PRIORITY 3
/*
* SPI driver system settings.
*/
#define LPC17xx_SPI_USE_SSP0 FALSE
#define LPC17xx_SPI_USE_SSP1 FALSE
#define LPC17xx_SPI_SSP0CLKDIV 1
#define LPC17xx_SPI_SSP1CLKDIV 1
#define LPC17xx_SPI_SSP0_IRQ_PRIORITY 5
#define LPC17xx_SPI_SSP1_IRQ_PRIORITY 5
/*
* RTC driver system settings.
*/
#define LPC17xx_RTC_IS_CALENDAR TRUE
#define LPC17xx_RTC_USE_ALARM TRUE
#define LPC17xx_RTC_IRQ_PRIORITY 3
/*
* CAN driver system settings.
*/
#define LPC17xx_CAN_USE_CAN1 TRUE
#define LPC17xx_CAN_USE_CAN2 TRUE
#define LPC17xx_CAN_IRQ_PRIORITY 11
#define LPC17xx_CAN_USE_LOCAL_SELF_TEST FALSE
#define LPC17xx_CAN_USE_FILTER TRUE

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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/boards/EA_LPCXPRESSO_LPC1769/board.mk
include $(CHIBIOS)/os/hal/platforms/LPC17xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC17xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/LPC1769.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m3
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS = -DLPC17XX -D__NEWLIB__
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN TRUE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/*
* Local self test mode.
*/
static const CANConfig cancfg = {
CANMOD_STM,
CANBTR_SJW(0) | CANBTR_TESG2(1) |
CANBTR_TESG1(8) | CANBTR_BRP(20)
};
/*
* Receiver thread.
*/
static WORKING_AREA(can_rx1_wa, 256);
static msg_t can_rx(void *p) {
EventListener el;
CANRxFrame rxmsg;
(void)p;
chRegSetThreadName("receiver");
chEvtRegister(&CAND1.rxfull_event, &el, 0);
while(!chThdShouldTerminate()) {
if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0)
continue;
while (canReceive(&CAND1, CAN_ANY_MAILBOX,
&rxmsg, TIME_IMMEDIATE) == RDY_OK) {
/* Process message.*/
palTogglePad(GPIO0, GPIO0_LED2_RED);
}
}
chEvtUnregister(&CAND1.rxfull_event, &el);
return 0;
}
/*
* Transmitter thread.
*/
static WORKING_AREA(can_tx_wa, 256);
static msg_t can_tx(void * p) {
CANTxFrame txmsg;
(void)p;
chRegSetThreadName("transmitter");
txmsg.IDE = CAN_IDE_EXT;
txmsg.EID = 0x01234567;
txmsg.RTR = CAN_RTR_DATA;
txmsg.DLC = 8;
txmsg.data32[0] = 0x55AA55AA;
txmsg.data32[1] = 0x00FF00FF;
while (!chThdShouldTerminate()) {
canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100));
chThdSleepMilliseconds(500);
}
return 0;
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the CAN drivers 1.
*/
canStart(&CAND1, &cancfg);
/*
* Starting the transmitter and receiver threads.
*/
chThdCreateStatic(can_rx1_wa, sizeof(can_rx1_wa), NORMALPRIO + 7,
can_rx, NULL);
chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7,
can_tx, NULL);
/*
* Normal main() thread activity, in this demo it does nothing.
*/
while (TRUE) {
chThdSleepMilliseconds(500);
}
return 0;
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* LPC17xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*
* IRQ priorities:
* 7...0 Lowest...highest.
*/
/*
* HAL driver system settings.
*/
#define LPC17xx_MAINOSC_ENABLE TRUE
#define LPC17xx_SYSCLK_SELECT CLKSRCSEL_MAINOSC
#define LPC17xx_MAINPLL_ENABLE TRUE
#define LPC17xx_MAINPLL_MUL 30
#define LPC17xx_MAINPLL_PREDIV 1
#define LPC17xx_USBPLL_ENABLE FALSE
#define LPC17xx_USBPLL_MUL 4
#define LPC17xx_USBPLL_DIV 4
#define LPC17xx_CCLK_DIV 3
#define LPC17xx_PCLK_SELECT PCLKSEL_CCLK
#define LPC17xx_CLKOUT_ENABLE FALSE
#define LPC17xx_CLKOUT_DIV 4
#define LPC17xx_CLKOUT_SELECT CLKOUTSEL_CCLK
/*
* GPT driver system settings.
*/
#define LPC17xx_GPT_USE_TIM0 TRUE
#define LPC17xx_GPT_USE_TIM1 TRUE
#define LPC17xx_GPT_USE_TIM2 TRUE
#define LPC17xx_GPT_USE_TIM3 TRUE
#define LPC17xx_GPT_TIM0_IRQ_PRIORITY 2
#define LPC17xx_GPT_TIM1_IRQ_PRIORITY 6
#define LPC17xx_GPT_TIM2_IRQ_PRIORITY 2
#define LPC17xx_GPT_TIM3_IRQ_PRIORITY 2
/*
* SERIAL driver system settings.
*/
#define LPC17xx_SERIAL_USE_UART0 TRUE
#define LPC17xx_SERIAL_USE_UART1 FALSE
#define LPC17xx_SERIAL_USE_UART2 FALSE
#define LPC17xx_SERIAL_USE_UART3 FALSE
#define LPC17xx_SERIAL_FIFO_PRELOAD 16
#define LPC17xx_SERIAL_UART0_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART1_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART2_IRQ_PRIORITY 3
#define LPC17xx_SERIAL_UART3_IRQ_PRIORITY 3
/*
* I2C driver system settings.
*/
#define LPC17xx_I2C_USE_I2C0 FALSE
#define LPC17xx_I2C_USE_I2C1 TRUE
#define LPC17xx_I2C_USE_I2C2 FALSE
#define LPC17xx_I2C_I2C0_IRQ_PRIORITY 3
#define LPC17xx_I2C_I2C1_IRQ_PRIORITY 3
#define LPC17xx_I2C_I2C2_IRQ_PRIORITY 3
/*
* SPI driver system settings.
*/
#define LPC17xx_SPI_USE_SSP0 FALSE
#define LPC17xx_SPI_USE_SSP1 FALSE
#define LPC17xx_SPI_SSP0CLKDIV 1
#define LPC17xx_SPI_SSP1CLKDIV 1
#define LPC17xx_SPI_SSP0_IRQ_PRIORITY 5
#define LPC17xx_SPI_SSP1_IRQ_PRIORITY 5
/*
* RTC driver system settings.
*/
#define LPC17xx_RTC_IS_CALENDAR TRUE
#define LPC17xx_RTC_USE_ALARM TRUE
#define LPC17xx_RTC_IRQ_PRIORITY 3
/*
* CAN driver system settings.
*/
#define LPC17xx_CAN_USE_CAN1 TRUE
#define LPC17xx_CAN_USE_CAN2 FALSE
#define LPC17xx_CAN_IRQ_PRIORITY 11
#define LPC17xx_CAN_USE_LOCAL_SELF_TEST TRUE
#define LPC17XX_CAN_USE_FILTER FALSE