Changes to the DAC driver, not tested yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7935 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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f112ffa1e6
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@ -51,7 +51,7 @@
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STM32_DMA_GETCHANNEL(STM32_DAC2_CH2_DMA_STREAM, \
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STM32_DAC2_CH2_DMA_CHN)
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#define CHANNEL_DATA_OFFSET 12
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#define CHANNEL_DATA_OFFSET 12U
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/*===========================================================================*/
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/* Driver exported variables. */
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@ -81,6 +81,72 @@ DACDriver DACD4;
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/* Driver local variables. */
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/*===========================================================================*/
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static const DACConfig default_config = {0};
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#if STM32_DAC_USE_DAC1_CH1 == TRUE
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static const dacparams_t dma1_ch1_params = {
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dac: DAC1,
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC1_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC1_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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dac: DAC1,
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC1_CH2_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC2_CH1 == TRUE
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static const dacparams_t dma2_ch1_params = {
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dac: DAC2,
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC2_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC2_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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dac: DAC2,
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC2_CH2_IRQ_PRIORITY
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};
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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@ -126,54 +192,22 @@ void dac_lld_init(void) {
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#if STM32_DAC_USE_DAC1_CH1
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dacObjectInit(&DACD1);
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DACD1.dac = DAC1;
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DACD1.dma = STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM);
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DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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DACD1.params = &dma1_ch1_params;
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#endif
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#if STM32_DAC_USE_DAC1_CH2
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dacObjectInit(&DACD2);
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DACD2.dac = DAC1;
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DACD2.dma = STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM);
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DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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DACD2.params = &dma1_ch2_params;
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#endif
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#if STM32_DAC_USE_DAC2_CH1
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dacObjectInit(&DACD3);
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DACD3.dac = DAC2;
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DACD3.dma = STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM);
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DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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DACD3.params = &dma2_ch1_params;
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#endif
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#if STM32_DAC_USE_DAC2_CH2
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dacObjectInit(&DACD4);
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DACD4.dac = DAC2;
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DACD4.dma = STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM);
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DACD4.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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DACD4.params = &dma2_ch2_params;
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#endif
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}
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@ -185,108 +219,129 @@ void dac_lld_init(void) {
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* @notapi
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*/
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void dac_lld_start(DACDriver *dacp) {
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uint32_t cr, regshift, dataoffset;
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bool b;
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/* If the application does not provide a configuration structure then a
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default is used.*/
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if (dacp->config == NULL) {
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dacp->config = &default_config;
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}
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/* If the driver is in DAC_STOP state then a full initialization is
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required.*/
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if (dacp->state == DAC_STOP) {
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/* Allocating the DMA channel.*/
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b = dmaStreamAllocate(dacp->params->dma, dacp->params->dmairqprio,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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/* Enabling the clock source.*/
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#if STM32_DAC_USE_DAC1_CH1
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if (&DACD1 == dacp) {
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if (dacp->state == DAC_STOP) {
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b = dmaStreamAllocate(dacp->dma, STM32_DAC1_CH1_IRQ_PRIORITY,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC1(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = 0;
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regshift = 0;
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}
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rccEnableDAC1(false);
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}
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#endif
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#if STM32_DAC_USE_DAC1_CH2
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if (&DACD2 == dacp) {
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if (dacp->state == DAC_STOP) {
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b = dmaStreamAllocate(dacp->dma, STM32_DAC1_CH2_IRQ_PRIORITY,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC1(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = CHANNEL_DATA_OFFSET;
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regshift = 16;
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rccEnableDAC1(false);
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}
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#endif
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#if STM32_DAC_USE_DAC2_CH1
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if (&DACD3 == dacp) {
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if (dacp->state == DAC_STOP) {
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b = dmaStreamAllocate(dacp->dma, STM32_DAC2_CH1_IRQ_PRIORITY,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC2(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = 0;
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regshift = 0;
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rccEnableDAC2(false);
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}
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#endif
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#if STM32_DAC_USE_DAC2_CH2
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if (&DACD3 == dacp) {
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if (dacp->state == DAC_STOP) {
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b = dmaStreamAllocate(dacp->dma, STM32_DAC2_CH2_IRQ_PRIORITY,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC2(false);
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}
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rccEnableDAC2(false);
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}
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#endif
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}
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/* Channel-specific parameters.*/
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dataoffset = CHANNEL_DATA_OFFSET;
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regshift = 16;
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/* DAC initially disabled.*/
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#if STM32_DAC_DUAL_MODE == FALSE
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dacp->params->dac->CR = dacp->params->regmask;
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#else
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dacp->params->dac->CR = 0U;
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#endif
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}
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/**
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* @brief Deactivates the DAC peripheral.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_stop(DACDriver *dacp) {
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/* If in ready state then disables the DAC clock.*/
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if (dacp->state == DAC_READY) {
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/* DMA channel released.*/
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dmaStreamRelease(dacp->params->dma);
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#if STM32_DAC_USE_DAC1_CH1
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if (&DACD1 == dacp) {
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dacp->params->dac->CR &= ~DAC_CR_EN1;
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC1(false);
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}
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}
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#endif
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/* DAC configuration.*/
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#if STM32_DAC_DUAL_MODE == FALSE
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cr = DAC_CR_DMAEN1 | (dacp->config->cr_tsel << 3) |
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DAC_CR_TEN1 | DAC_CR_EN1;
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dacp->dac->CR = (dacp->dac->CR & ~(0x0000FFFF << regshift)) |
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(cr << regshift);
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#else
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/* TODO: Dual.*/
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#if STM32_DAC_USE_DAC1_CH2
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if (&DACD2 == dacp) {
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dacp->params->dac->CR &= ~DAC_CR_EN2;
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC1(false);
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}
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}
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#endif
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}
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}
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/**
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* @brief Starts a DAC conversion.
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* @details Starts an asynchronous conversion operation.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_start_conversion(DACDriver *dacp) {
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uint32_t cr, dmamode;
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#if STM32_DAC_DUAL_MODE == FALSE
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switch (dacp->config->dhrm) {
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/* Sets the DAC data register */
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case DAC_DHRM_12BIT_RIGHT:
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dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
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dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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*(&dacp->dac->DHR12R1 + dataoffset) = (uint32_t)dacp->config->sample;
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break;
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case DAC_DHRM_12BIT_LEFT:
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dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
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dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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*(&dacp->dac->DHR12L1 + dataoffset) = (uint32_t)dacp->config->sample;
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break;
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case DAC_DHRM_8BIT_RIGHT:
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dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
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dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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*(&dacp->dac->DHR8R1 + dataoffset) = (uint32_t)dacp->config->sample;
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break;
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default:
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chDbgAssert(false, "unexpected DAC mode");
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break;
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switch (dacp->grpp->dhrm) {
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/* Sets the DAC data register */
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case DAC_DHRM_12BIT_RIGHT:
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dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12R1 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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break;
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case DAC_DHRM_12BIT_LEFT:
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dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12L1 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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break;
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case DAC_DHRM_8BIT_RIGHT:
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dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8R1 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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break;
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default:
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chDbgAssert(false, "unexpected DAC mode");
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break;
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}
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#else
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#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
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@ -307,61 +362,23 @@ void dac_lld_start(DACDriver *dacp) {
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break;
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#endif
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#endif
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}
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/**
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* @brief Deactivates the DAC peripheral.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_stop(DACDriver *dacp) {
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/* If in ready state then disables the DAC clock.*/
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if (dacp->state == DAC_READY) {
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/* DMA channel released.*/
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dmaStreamRelease(dacp->dma);
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#if STM32_DAC_USE_DAC1_CH1
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if (&DACD1 == dacp) {
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dacp->dac->CR &= ~DAC_CR_EN1;
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if ((dacp->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC1(false);
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}
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}
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#endif
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#if STM32_DAC_USE_DAC1_CH2
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if (&DACD2 == dacp) {
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dacp->dac->CR &= ~DAC_CR_EN2;
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if ((dacp->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC1(false);
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}
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}
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#endif
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}
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}
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/**
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* @brief Starts a DAC conversion.
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* @details Starts an asynchronous conversion operation.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_start_conversion(DACDriver *dacp) {
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dmaStreamSetMemory0(dacp->dma, dacp->samples);
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dmaStreamSetTransactionSize(dacp->dma, dacp->depth);
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dmaStreamSetMode(dacp->dma, dacp->dmamode |
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dmaStreamSetMemory0(dacp->params->dma, dacp->samples);
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dmaStreamSetTransactionSize(dacp->params->dma, dacp->depth);
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dmaStreamSetMode(dacp->params->dma, dmamode |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
|
||||
dmaStreamEnable(dacp->dma);
|
||||
dmaStreamEnable(dacp->params->dma);
|
||||
|
||||
/* DAC configuration.*/
|
||||
#if STM32_DAC_DUAL_MODE == FALSE
|
||||
cr = DAC_CR_DMAEN1 | (dacp->grpp->cr_tsel << 3) |
|
||||
DAC_CR_TEN1 | DAC_CR_EN1;
|
||||
dacp->params->dac->CR = (dacp->params->dac->CR & dacp->params->regmask) |
|
||||
(cr << dacp->params->regshift);
|
||||
#else
|
||||
/* TODO: Dual.*/
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
@ -377,7 +394,12 @@ void dac_lld_start_conversion(DACDriver *dacp) {
|
|||
*/
|
||||
void dac_lld_stop_conversion(DACDriver *dacp) {
|
||||
|
||||
dmaStreamDisable(dacp->dma);
|
||||
dmaStreamDisable(dacp->params->dma);
|
||||
#if STM32_DAC_DUAL_MODE == FALSE
|
||||
dacp->params->dac->CR = dacp->params->regmask;
|
||||
#else
|
||||
dacp->params->dac->CR = 0U;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_DAC */
|
||||
|
|
|
@ -220,6 +220,40 @@
|
|||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DAC channel parameters type.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Pointer to the DAC registers block.
|
||||
*/
|
||||
DAC_TypeDef *dac;
|
||||
/**
|
||||
* @brief DAC data registers offset.
|
||||
*/
|
||||
uint32_t dataoffset;
|
||||
/**
|
||||
* @brief DAC CR register bit offset.
|
||||
*/
|
||||
uint32_t regshift;
|
||||
/**
|
||||
* @brief DAC CR register mask.
|
||||
*/
|
||||
uint32_t regmask;
|
||||
/**
|
||||
* @brief Associated DMA.
|
||||
*/
|
||||
const stm32_dma_stream_t *dma;
|
||||
/**
|
||||
* @brief Mode bits for the DMA.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
/**
|
||||
* @brief DMA channel IRQ priority.
|
||||
*/
|
||||
uint32_t dmairqprio;
|
||||
} dacparams_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an DAC driver.
|
||||
*/
|
||||
|
@ -292,17 +326,6 @@ typedef struct {
|
|||
*/
|
||||
dacerrorcallback_t error_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
} DACConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Initial sample to be presented on outputs.
|
||||
*/
|
||||
dacsample_t sample;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief DAC data holding register mode.
|
||||
*/
|
||||
|
@ -314,6 +337,14 @@ typedef struct {
|
|||
* other fields are handled internally.
|
||||
*/
|
||||
uint32_t cr_tsel;
|
||||
} DACConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/* End of the mandatory fields.*/
|
||||
uint32_t dummy;
|
||||
} DACConfig;
|
||||
|
||||
/**
|
||||
|
@ -357,17 +388,9 @@ struct DACDriver {
|
|||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the DAC registers block.
|
||||
* @brief DAC channel parameters.
|
||||
*/
|
||||
DAC_TypeDef *dac;
|
||||
/**
|
||||
* @brief Transmit DMA stream.
|
||||
*/
|
||||
const stm32_dma_stream_t *dma;
|
||||
/**
|
||||
* @brief TX DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
const dacparams_t *params;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
|
@ -84,13 +84,15 @@ void dacObjectInit(DACDriver *dacp) {
|
|||
* @brief Configures and activates the DAC peripheral.
|
||||
*
|
||||
* @param[in] dacp pointer to the @p DACDriver object
|
||||
* @param[in] config pointer to the @p DACConfig object
|
||||
* @param[in] config pointer to the @p DACConfig object, it can be
|
||||
* @p NULL if the low level driver implementation
|
||||
* supports a default configuration
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void dacStart(DACDriver *dacp, const DACConfig *config) {
|
||||
|
||||
osalDbgCheck((dacp != NULL) && (config != NULL));
|
||||
osalDbgCheck(dacp != NULL);
|
||||
|
||||
osalSysLock();
|
||||
|
||||
|
|
Loading…
Reference in New Issue