git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5183 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
parent
2211987fdb
commit
446f34f336
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@ -56,11 +56,6 @@ const PALConfig pal_default_config = {
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void __early_init(void) {
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void __early_init(void) {
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spc_early_init();
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spc_early_init();
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/* SWT disabled.*/
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SWT.SR.R = 0xC520;
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SWT.SR.R = 0xD928;
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SWT.CR.R = 0xFF00000A;
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}
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}
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/*
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/*
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@ -30,6 +30,7 @@
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*/
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*/
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#define SPC5_NO_INIT FALSE
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#define SPC5_NO_INIT FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_DISABLE_WATCHDOG TRUE
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#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
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#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
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#define SPC5_FMPLL0_IDF_VALUE 5
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#define SPC5_FMPLL0_IDF_VALUE 5
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#define SPC5_FMPLL0_NDIV_VALUE 60
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#define SPC5_FMPLL0_NDIV_VALUE 60
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@ -151,3 +152,15 @@
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/*
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/*
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* SERIAL driver system settings.
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* SERIAL driver system settings.
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*/
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*/
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#define SPC5_SERIAL_USE_LINFLEX0 TRUE
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#define SPC5_SERIAL_USE_LINFLEX1 TRUE
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#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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@ -109,6 +109,32 @@ void spc_early_init(void) {
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#if !SPC5_NO_INIT
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#if !SPC5_NO_INIT
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#if SPC5_DISABLE_WATCHDOG
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/* SWT disabled.*/
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SWT.SR.R = 0xC520;
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SWT.SR.R = 0xD928;
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SWT.CR.R = 0xFF00000A;
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#endif
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/* Enabling peripheral bridges to allow any operation.*/
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AIPS.MPROT.R = 0x77777777;
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AIPS.PACR0_7.R = 0;
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AIPS.PACR8_15.R = 0;
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AIPS.PACR16_23.R = 0;
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AIPS.PACR24_31.R = 0;
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AIPS.OPACR0_7.R = 0;
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AIPS.OPACR8_15.R = 0;
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AIPS.OPACR16_23.R = 0;
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AIPS.OPACR24_31.R = 0;
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AIPS.OPACR32_39.R = 0;
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AIPS.OPACR40_47.R = 0;
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AIPS.OPACR48_55.R = 0;
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AIPS.OPACR56_63.R = 0;
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AIPS.OPACR64_71.R = 0;
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AIPS.OPACR72_79.R = 0;
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AIPS.OPACR80_87.R = 0;
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AIPS.OPACR88_95.R = 0;
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/* SSCM initialization. Setting up the most restrictive handling of
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/* SSCM initialization. Setting up the most restrictive handling of
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invalid accesses to peripherals.*/
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invalid accesses to peripherals.*/
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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@ -241,6 +241,13 @@
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#endif
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#endif
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/**
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* @brief Disables the watchdog on start.
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*/
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#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
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#define SPC5_DISABLE_WATCHDOG TRUE
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#endif
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/**
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/**
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* @brief FMPLL0 Clock source.
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* @brief FMPLL0 Clock source.
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*/
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*/
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@ -331,44 +331,6 @@ _coreinit:
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mtspr 624, %r3 /* MAS0 */
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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tlbwe
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/*
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* PBRIDGE programmed to allow all accesses from user mode.
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*/
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lis %r7, 0xFFF0
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lis %r3, 0x7777
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ori %r3, %r3, 0x7777
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stw %r3, 0(%r7) /* MPROT */
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li %r3, 0
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stw %r3, 32(%r7) /* PACR */
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stw %r3, 36(%r7)
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stw %r3, 40(%r7)
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stw %r3, 44(%r7)
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stw %r3, 64(%r7) /* OPACR */
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stw %r3, 68(%r7)
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stw %r3, 72(%r7)
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stw %r3, 76(%r7)
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stw %r3, 80(%r7)
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stw %r3, 84(%r7)
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stw %r3, 88(%r7)
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stw %r3, 92(%r7)
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stw %r3, 96(%r7)
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stw %r3, 100(%r7)
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stw %r3, 104(%r7)
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stw %r3, 108(%r7)
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e_lis r6,0xfff3
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e_or2i r6,0x8010
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e_li r7,0xC520
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se_stw r7,0x0(r6)
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e_li r7,0xD928
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se_stw r7,0x0(r6)
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e_lis r6,0xfff3
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e_or2i r6,0x8000
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e_lis r7,0xff00
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e_or2i r7,0x10A
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se_stw r7,0x0(r6) /* # WEN = 0 */
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/*
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* order to initialize the ECC detection hardware, this is going to
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