andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3062 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-06-19 11:35:07 +00:00
parent ec3ca5b4e6
commit 45765c3f76
2 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
os/hal/platforms/STM32L1xx/hal_lld.c
View File

@ -90,6 +90,9 @@ void hal_lld_init(void) {
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* Core voltage setup.*/
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */

4
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -59,9 +59,9 @@
/* PWR_CR register bits definitions.*/
#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
#define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
#define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */
#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
/* RCC_CR register bits definitions.*/
#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */