From 460ae80f9260fbea7c6b4d94e99a40acfcc018bc Mon Sep 17 00:00:00 2001 From: pcirillo Date: Wed, 15 May 2013 13:42:41 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5738 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/SPC563Mxx/spc563m_registry.h | 43 + os/hal/platforms/SPC564Axx/spc564a_registry.h | 59 ++ os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c | 907 +++++++++++++++++ os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h | 443 ++++++++ os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c | 951 ++++++++++++++++++ os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h | 457 +++++++++ .../platforms/SPC5xx/eMIOS200_v1/spc5_emios.c | 117 +++ .../platforms/SPC5xx/eMIOS200_v1/spc5_emios.h | 114 +++ testhal/SPC563Mxx/ICU-PWM/.cproject | 51 + testhal/SPC563Mxx/ICU-PWM/.project | 38 + testhal/SPC563Mxx/ICU-PWM/Makefile | 168 ++++ testhal/SPC563Mxx/ICU-PWM/chconf.h | 536 ++++++++++ testhal/SPC563Mxx/ICU-PWM/halconf.h | 367 +++++++ testhal/SPC563Mxx/ICU-PWM/main.c | 147 +++ testhal/SPC563Mxx/ICU-PWM/mcuconf.h | 100 ++ testhal/SPC563Mxx/ICU-PWM/readme.txt | 27 + testhal/SPC564Axx/ICU_PWM/Makefile | 121 +++ testhal/SPC564Axx/ICU_PWM/chconf.h | 536 ++++++++++ testhal/SPC564Axx/ICU_PWM/halconf.h | 367 +++++++ testhal/SPC564Axx/ICU_PWM/main.c | 146 +++ testhal/SPC564Axx/ICU_PWM/mcuconf.h | 108 ++ testhal/SPC564Axx/ICU_PWM/readme.txt | 27 + 22 files changed, 5830 insertions(+) create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c create mode 100644 os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h create mode 100644 testhal/SPC563Mxx/ICU-PWM/.cproject create mode 100644 testhal/SPC563Mxx/ICU-PWM/.project create mode 100644 testhal/SPC563Mxx/ICU-PWM/Makefile create mode 100644 testhal/SPC563Mxx/ICU-PWM/chconf.h create mode 100644 testhal/SPC563Mxx/ICU-PWM/halconf.h create mode 100644 testhal/SPC563Mxx/ICU-PWM/main.c create mode 100644 testhal/SPC563Mxx/ICU-PWM/mcuconf.h create mode 100644 testhal/SPC563Mxx/ICU-PWM/readme.txt create mode 100644 testhal/SPC564Axx/ICU_PWM/Makefile create mode 100644 testhal/SPC564Axx/ICU_PWM/chconf.h create mode 100644 testhal/SPC564Axx/ICU_PWM/halconf.h create mode 100644 testhal/SPC564Axx/ICU_PWM/main.c create mode 100644 testhal/SPC564Axx/ICU_PWM/mcuconf.h create mode 100644 testhal/SPC564Axx/ICU_PWM/readme.txt diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h index f77635840..bf3cca0d5 100644 --- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h +++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h @@ -74,6 +74,49 @@ /* SIU attributes.*/ #define SPC5_HAS_SIU TRUE #define SPC5_SIU_SUPPORTS_PORTS FALSE + +/* EMIOS attributes.*/ +#define SPC5_HAS_EMIOS TRUE + +#define SPC5_EMIOS_NUM_CHANNELS 16 + +#define SPC5_EMIOS_FLAG_F0_HANDLER vector51 +#define SPC5_EMIOS_FLAG_F1_HANDLER vector52 +#define SPC5_EMIOS_FLAG_F2_HANDLER vector53 +#define SPC5_EMIOS_FLAG_F3_HANDLER vector54 +#define SPC5_EMIOS_FLAG_F4_HANDLER vector55 +#define SPC5_EMIOS_FLAG_F5_HANDLER vector56 +#define SPC5_EMIOS_FLAG_F6_HANDLER vector57 +#define SPC5_EMIOS_FLAG_F8_HANDLER vector59 +#define SPC5_EMIOS_FLAG_F9_HANDLER vector60 +#define SPC5_EMIOS_FLAG_F10_HANDLER vector61 +#define SPC5_EMIOS_FLAG_F11_HANDLER vector62 +#define SPC5_EMIOS_FLAG_F12_HANDLER vector63 +#define SPC5_EMIOS_FLAG_F13_HANDLER vector64 +#define SPC5_EMIOS_FLAG_F14_HANDLER vector65 +#define SPC5_EMIOS_FLAG_F15_HANDLER vector66 +#define SPC5_EMIOS_FLAG_F23_HANDLER vector209 +#define SPC5_EMIOS_FLAG_F0_NUMBER 51 +#define SPC5_EMIOS_FLAG_F1_NUMBER 52 +#define SPC5_EMIOS_FLAG_F2_NUMBER 53 +#define SPC5_EMIOS_FLAG_F3_NUMBER 54 +#define SPC5_EMIOS_FLAG_F4_NUMBER 55 +#define SPC5_EMIOS_FLAG_F5_NUMBER 56 +#define SPC5_EMIOS_FLAG_F6_NUMBER 57 +#define SPC5_EMIOS_FLAG_F8_NUMBER 59 +#define SPC5_EMIOS_FLAG_F9_NUMBER 60 +#define SPC5_EMIOS_FLAG_F10_NUMBER 61 +#define SPC5_EMIOS_FLAG_F11_NUMBER 62 +#define SPC5_EMIOS_FLAG_F12_NUMBER 63 +#define SPC5_EMIOS_FLAG_F13_NUMBER 64 +#define SPC5_EMIOS_FLAG_F14_NUMBER 65 +#define SPC5_EMIOS_FLAG_F15_NUMBER 66 +#define SPC5_EMIOS_FLAG_F23_NUMBER 209 + +#define SPC5_EMIOS_CLK (64000000 / \ + SPC5_EMIOS_GLOBAL_PRESCALER) +#define SPC5_EMIOS_ENABLE_CLOCK() +#define SPC5_EMIOS_DISABLE_CLOCK() /** @} */ #endif /* _SPC563M_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index 6d84e6354..6002453c9 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -57,6 +57,65 @@ /* SIU attributes.*/ #define SPC5_HAS_SIU TRUE #define SPC5_SIU_SUPPORTS_PORTS FALSE + +/* EMIOS attributes.*/ +#define SPC5_HAS_EMIOS TRUE + +#define SPC5_EMIOS_NUM_CHANNELS 24 + +#define SPC5_EMIOS_FLAG_F0_HANDLER vector51 +#define SPC5_EMIOS_FLAG_F1_HANDLER vector52 +#define SPC5_EMIOS_FLAG_F2_HANDLER vector53 +#define SPC5_EMIOS_FLAG_F3_HANDLER vector54 +#define SPC5_EMIOS_FLAG_F4_HANDLER vector55 +#define SPC5_EMIOS_FLAG_F5_HANDLER vector56 +#define SPC5_EMIOS_FLAG_F6_HANDLER vector57 +#define SPC5_EMIOS_FLAG_F7_HANDLER vector58 +#define SPC5_EMIOS_FLAG_F8_HANDLER vector59 +#define SPC5_EMIOS_FLAG_F9_HANDLER vector60 +#define SPC5_EMIOS_FLAG_F10_HANDLER vector61 +#define SPC5_EMIOS_FLAG_F11_HANDLER vector62 +#define SPC5_EMIOS_FLAG_F12_HANDLER vector63 +#define SPC5_EMIOS_FLAG_F13_HANDLER vector64 +#define SPC5_EMIOS_FLAG_F14_HANDLER vector65 +#define SPC5_EMIOS_FLAG_F15_HANDLER vector66 +#define SPC5_EMIOS_FLAG_F16_HANDLER vector202 +#define SPC5_EMIOS_FLAG_F17_HANDLER vector203 +#define SPC5_EMIOS_FLAG_F18_HANDLER vector204 +#define SPC5_EMIOS_FLAG_F19_HANDLER vector205 +#define SPC5_EMIOS_FLAG_F20_HANDLER vector206 +#define SPC5_EMIOS_FLAG_F21_HANDLER vector207 +#define SPC5_EMIOS_FLAG_F22_HANDLER vector208 +#define SPC5_EMIOS_FLAG_F23_HANDLER vector209 +#define SPC5_EMIOS_FLAG_F0_NUMBER 51 +#define SPC5_EMIOS_FLAG_F1_NUMBER 52 +#define SPC5_EMIOS_FLAG_F2_NUMBER 53 +#define SPC5_EMIOS_FLAG_F3_NUMBER 54 +#define SPC5_EMIOS_FLAG_F4_NUMBER 55 +#define SPC5_EMIOS_FLAG_F5_NUMBER 56 +#define SPC5_EMIOS_FLAG_F6_NUMBER 57 +#define SPC5_EMIOS_FLAG_F7_NUMBER 58 +#define SPC5_EMIOS_FLAG_F8_NUMBER 59 +#define SPC5_EMIOS_FLAG_F9_NUMBER 60 +#define SPC5_EMIOS_FLAG_F10_NUMBER 61 +#define SPC5_EMIOS_FLAG_F11_NUMBER 62 +#define SPC5_EMIOS_FLAG_F12_NUMBER 63 +#define SPC5_EMIOS_FLAG_F13_NUMBER 64 +#define SPC5_EMIOS_FLAG_F14_NUMBER 65 +#define SPC5_EMIOS_FLAG_F15_NUMBER 66 +#define SPC5_EMIOS_FLAG_F16_NUMBER 202 +#define SPC5_EMIOS_FLAG_F17_NUMBER 203 +#define SPC5_EMIOS_FLAG_F18_NUMBER 204 +#define SPC5_EMIOS_FLAG_F19_NUMBER 205 +#define SPC5_EMIOS_FLAG_F20_NUMBER 206 +#define SPC5_EMIOS_FLAG_F21_NUMBER 207 +#define SPC5_EMIOS_FLAG_F22_NUMBER 208 +#define SPC5_EMIOS_FLAG_F23_NUMBER 209 + +#define SPC5_EMIOS_CLK (64000000 / \ + SPC5_EMIOS_GLOBAL_PRESCALER) +#define SPC5_EMIOS_ENABLE_CLOCK() +#define SPC5_EMIOS_DISABLE_CLOCK() /** @} */ #endif /* _SPC563M_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c new file mode 100644 index 000000000..b4b9fce01 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c @@ -0,0 +1,907 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/icu_lld.c + * @brief SPC5xx low level icu driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the unified channel eMIOS_CH0 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH0 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD2 allocates the unified channel eMIOS_CH1 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH1 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD3 allocates the unified channel eMIOS_CH2 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH2 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the unified channel eMIOS_CH3 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH3 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the unified channel eMIOS_CH4 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH4 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD6 driver identifier. + * @note The driver ICUD6 allocates the unified channel eMIOS_CH5 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH5 || defined(__DOXYGEN__) +ICUDriver ICUD6; +#endif + +/** + * @brief ICUD7 driver identifier. + * @note The driver ICUD7 allocates the unified channel eMIOS_CH6 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH6 || defined(__DOXYGEN__) +ICUDriver ICUD7; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the unified channel eMIOS_CH8 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH8 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the unified channel eMIOS_CH7 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH7 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/** + * @brief ICUD10 driver identifier. + * @note The driver ICUD10 allocates the unified channel eMIOS_CH16 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH16 || defined(__DOXYGEN__) +ICUDriver ICUD10; +#endif + +/** + * @brief ICUD11 driver identifier. + * @note The driver ICUD11 allocates the unified channel eMIOS_CH17 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH17 || defined(__DOXYGEN__) +ICUDriver ICUD11; +#endif + +/** + * @brief ICUD12 driver identifier. + * @note The driver ICUD12 allocates the unified channel eMIOS_CH18 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH18 || defined(__DOXYGEN__) +ICUDriver ICUD12; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Width and Period registers. + */ +uint32_t width; +uint32_t period; + +/** + * @brief A2 temp registers. + */ +uint32_t A2_1, A2_2, A2_3; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ICU IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + + uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R; + + if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC; + _icu_isr_invoke_overflow_cb(icup); + } + if (sr && EMIOSS_FLAG){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC; + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } + } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } + } + } + if(sr && EMIOSS_OVR){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC; + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS_CH0 +#if !defined(SPC5_EMIOS_FLAG_F0_HANDLER) +#error "SPC5_EMIOS_FLAG_F0_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 0 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ + +#if SPC5_ICU_USE_EMIOS_CH1 +#if !defined(SPC5_EMIOS_FLAG_F1_HANDLER) +#error "SPC5_EMIOS_FLAG_F1_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ + +#if SPC5_ICU_USE_EMIOS_CH2 +#if !defined(SPC5_EMIOS_FLAG_F2_HANDLER) +#error "SPC5_EMIOS_FLAG_F2_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ + +#if SPC5_ICU_USE_EMIOS_CH3 +#if !defined(SPC5_EMIOS_FLAG_F3_HANDLER) +#error "SPC5_EMIOS_FLAG_F3_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ + +#if SPC5_ICU_USE_EMIOS_CH4 +#if !defined(SPC5_EMIOS_FLAG_F4_HANDLER) +#error "SPC5_EMIOS_FLAG_F4_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ + +#if SPC5_ICU_USE_EMIOS_CH5 +#if !defined(SPC5_EMIOS_FLAG_F5_HANDLER) +#error "SPC5_EMIOS_FLAG_F5_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ + +#if SPC5_ICU_USE_EMIOS_CH6 +#if !defined(SPC5_EMIOS_FLAG_F6_HANDLER) +#error "SPC5_EMIOS_FLAG_F6_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 6 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ + +#if SPC5_ICU_USE_EMIOS_CH7 +#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER) +#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 7 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F7_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ + +#if SPC5_ICU_USE_EMIOS_CH7 +#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER) +#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 8 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F8_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ + +#if SPC5_ICU_USE_EMIOS_CH16 +#if !defined(SPC5_EMIOS_FLAG_F16_HANDLER) +#error "SPC5_EMIOS_FLAG_F16_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 16 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F16_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD10); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ + +#if SPC5_ICU_USE_EMIOS_CH17 +#if !defined(SPC5_EMIOS_FLAG_F17_HANDLER) +#error "SPC5_EMIOS_FLAG_F17_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 17 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F17_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ + +#if SPC5_ICU_USE_EMIOS_CH18 +#if !defined(SPC5_EMIOS_FLAG_F18_HANDLER) +#error "SPC5_EMIOS_FLAG_F18_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 18 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F18_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + + /* Initialize A2 temp registers.*/ + A2_1 = 0U; + A2_2 = 0U; + A2_3 = 0U; + + /* eMIOSx channels initially all not in use.*/ + reset_emios_active_channels(); + +#if SPC5_ICU_USE_EMIOS_CH0 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.emiosp = &EMIOS; + ICUD1.ch_number = 0U; + ICUD1.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ + +#if SPC5_ICU_USE_EMIOS_CH1 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.emiosp = &EMIOS; + ICUD2.ch_number = 1U; + ICUD2.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ + +#if SPC5_ICU_USE_EMIOS_CH2 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.emiosp = &EMIOS; + ICUD3.ch_number = 2U; + ICUD3.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ + +#if SPC5_ICU_USE_EMIOS_CH3 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.emiosp = &EMIOS; + ICUD4.ch_number = 3U; + ICUD4.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ + +#if SPC5_ICU_USE_EMIOS_CH4 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.emiosp = &EMIOS; + ICUD5.ch_number = 4U; + ICUD5.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ + +#if SPC5_ICU_USE_EMIOS_CH5 + /* Driver initialization.*/ + icuObjectInit(&ICUD6); + ICUD6.emiosp = &EMIOS; + ICUD6.ch_number = 5U; + ICUD6.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ + +#if SPC5_ICU_USE_EMIOS_CH6 + /* Driver initialization.*/ + icuObjectInit(&ICUD7); + ICUD7.emiosp = &EMIOS; + ICUD7.ch_number = 6U; + ICUD7.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ + +#if SPC5_ICU_USE_EMIOS_CH8 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.emiosp = &EMIOS; + ICUD8.ch_number = 8U; + ICUD8.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ + +#if SPC5_ICU_USE_EMIOS_CH7 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.emiosp = &EMIOS; + ICUD9.ch_number = 7U; + ICUD9.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ + +#if SPC5_ICU_USE_EMIOS_CH16 + /* Driver initialization.*/ + icuObjectInit(&ICUD10); + ICUD10.emiosp = &EMIOS; + ICUD10.ch_number = 16U; + ICUD10.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ + +#if SPC5_ICU_USE_EMIOS_CH17 + /* Driver initialization.*/ + icuObjectInit(&ICUD11); + ICUD11.emiosp = &EMIOS; + ICUD11.ch_number = 17U; + ICUD11.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ + +#if SPC5_ICU_USE_EMIOS_CH18 + /* Driver initialization.*/ + icuObjectInit(&ICUD12); + ICUD12.emiosp = &EMIOS; + ICUD12.ch_number = 18U; + ICUD12.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + +#if SPC5_ICU_USE_EMIOS + +#if SPC5_EMIOS_NUM_CHANNELS == 16 + INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY; +#endif + +#if SPC5_EMIOS_NUM_CHANNELS == 24 + INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F7_NUMBER].R = SPC5_EMIOS_FLAG_F7_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F16_NUMBER].R = SPC5_EMIOS_FLAG_F16_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F17_NUMBER].R = SPC5_EMIOS_FLAG_F17_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F18_NUMBER].R = SPC5_EMIOS_FLAG_F18_PRIORITY; +#endif + +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "icu_lld_start(), #1", "too many channels"); + + if (icup->state == ICU_STOP) { + /* Enables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS_CH0 + if (&ICUD1 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ +#if SPC5_ICU_USE_EMIOS_CH1 + if (&ICUD2 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ +#if SPC5_ICU_USE_EMIOS_CH2 + if (&ICUD3 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ +#if SPC5_ICU_USE_EMIOS_CH3 + if (&ICUD4 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ +#if SPC5_ICU_USE_EMIOS_CH4 + if (&ICUD5 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ +#if SPC5_ICU_USE_EMIOS_CH5 + if (&ICUD6 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ +#if SPC5_ICU_USE_EMIOS_CH6 + if (&ICUD7 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ +#if SPC5_ICU_USE_EMIOS_CH8 + if (&ICUD8 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ +#if SPC5_ICU_USE_EMIOS_CH7 + if (&ICUD9 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ +#if SPC5_ICU_USE_EMIOS_CH16 + if (&ICUD10 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ +#if SPC5_ICU_USE_EMIOS_CH17 + if (&ICUD11 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ +#if SPC5_ICU_USE_EMIOS_CH18 + if (&ICUD12 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + + /* Set eMIOS Clock.*/ +#if SPC5_ICU_USE_EMIOS + active_emios_clock(icup, NULL); +#endif + + } + /* Configures the peripheral.*/ + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set clock prescaler and control register.*/ + uint32_t psc = (icup->clock / icup->config->frequency); + chDbgAssert((psc <= 4) && + ((psc * icup->config->frequency) == icup->clock) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "icu_lld_start(), #1", "invalid frequency"); + + icup->emiosp->CH[icup->ch_number].CCR.B.UCPREN = 0; + icup->emiosp->CH[icup->ch_number].CCR.R |= + EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | + EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC; + icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1; + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN; + + /* Set source polarity.*/ + if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){ + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL; + } else { + icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL; + } + + /* Direct pointers to the period and width registers in order to make + reading data faster from within callbacks.*/ + icup->pccrp = . + icup->wccrp = &width; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "icu_lld_stop(), #1", "too many channels"); + + if (icup->state == ICU_READY) { + + /* Disables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS_CH0 + if (&ICUD1 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ +#if SPC5_ICU_USE_EMIOS_CH1 + if (&ICUD2 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ +#if SPC5_ICU_USE_EMIOS_CH2 + if (&ICUD3 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ +#if SPC5_ICU_USE_EMIOS_CH3 + if (&ICUD4 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ +#if SPC5_ICU_USE_EMIOS_CH4 + if (&ICUD5 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ +#if SPC5_ICU_USE_EMIOS_CH5 + if (&ICUD6 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ +#if SPC5_ICU_USE_EMIOS_CH6 + if (&ICUD7 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ +#if SPC5_ICU_USE_EMIOS_CH8 + if (&ICUD8 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ +#if SPC5_ICU_USE_EMIOS_CH7 + if (&ICUD9 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ +#if SPC5_ICU_USE_EMIOS_CH16 + if (&ICUD10 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ +#if SPC5_ICU_USE_EMIOS_CH17 + if (&ICUD11 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ +#if SPC5_ICU_USE_EMIOS_CH18 + if (&ICUD12 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + + /* eMIOS clock deactivation.*/ +#if SPC5_ICU_USE_EMIOS + deactive_emios_clock(); +#endif + + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Active interrupts.*/ + if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \ + icup->config->overflow_cb != NULL) { + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U; + } + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h new file mode 100644 index 000000000..bc750d5f2 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h @@ -0,0 +1,443 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/icu_lld.h + * @brief SPC5xx low level icu driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH0) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH0 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH1) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH1 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH2) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH2 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH3) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH3 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH4) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH4 FALSE +#endif + +/** + * @brief ICUD6 driver enable switch. + * @details If set to @p TRUE the support for ICUD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH5) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH5 FALSE +#endif + +/** + * @brief ICUD7 driver enable switch. + * @details If set to @p TRUE the support for ICUD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH6) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH6 FALSE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH8) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH8 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH7) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH7 FALSE +#endif + +/** + * @brief ICUD10 driver enable switch. + * @details If set to @p TRUE the support for ICUD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH16) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH16 FALSE +#endif + +/** + * @brief ICUD11 driver enable switch. + * @details If set to @p TRUE the support for ICUD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH17) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH17 FALSE +#endif + +/** + * @brief ICUD12 driver enable switch. + * @details If set to @p TRUE the support for ICUD12 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH18) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH18 FALSE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F0_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F0_PRIORITY 7 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F1_PRIORITY 7 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F2_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F2_PRIORITY 7 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F3_PRIORITY 7 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F4_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F4_PRIORITY 7 +#endif + +/** + * @brief ICUD6 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F5_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F5_PRIORITY 7 +#endif + +/** + * @brief ICUD7 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F6_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F6_PRIORITY 7 +#endif + +/** + * @brief ICUD8 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F8_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F8_PRIORITY 7 +#endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F7_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F7_PRIORITY 7 +#endif + +/** + * @brief ICUD10 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F16_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F16_PRIORITY 7 +#endif + +/** + * @brief ICUD11 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F17_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F17_PRIORITY 7 +#endif + +/** + * @brief ICUD12 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F18_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F18_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS +#error "EMIOS not present in the selected device" +#endif + +#define SPC5_ICU_USE_EMIOS (SPC5_ICU_USE_EMIOS_CH0 || \ + SPC5_ICU_USE_EMIOS_CH1 || \ + SPC5_ICU_USE_EMIOS_CH2 || \ + SPC5_ICU_USE_EMIOS_CH3 || \ + SPC5_ICU_USE_EMIOS_CH4 || \ + SPC5_ICU_USE_EMIOS_CH5 || \ + SPC5_ICU_USE_EMIOS_CH6 || \ + SPC5_ICU_USE_EMIOS_CH7 || \ + SPC5_ICU_USE_EMIOS_CH8 || \ + SPC5_ICU_USE_EMIOS_CH16 || \ + SPC5_ICU_USE_EMIOS_CH17 || \ + SPC5_ICU_USE_EMIOS_CH18) + +#if !SPC5_ICU_USE_EMIOS +#error "ICU driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint32_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief eMIOSx channel number. + */ + uint32_t ch_number; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; + /** + * @brief CH Counter clock. + */ + uint32_t clock; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; + /** + * @brief CCR register used for width capture. + */ + volatile vuint32_t *wccrp; + /** + * @brief CCR register used for period capture. + */ + volatile vuint32_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS_CH0 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if SPC5_ICU_USE_EMIOS_CH1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if SPC5_ICU_USE_EMIOS_CH2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if SPC5_ICU_USE_EMIOS_CH3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if SPC5_ICU_USE_EMIOS_CH4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if SPC5_ICU_USE_EMIOS_CH5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD6; +#endif + +#if SPC5_ICU_USE_EMIOS_CH6 && !defined(__DOXYGEN__) +extern ICUDriver ICUD7; +#endif + +#if SPC5_ICU_USE_EMIOS_CH8 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#if SPC5_ICU_USE_EMIOS_CH7 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#if SPC5_ICU_USE_EMIOS_CH16 && !defined(__DOXYGEN__) +extern ICUDriver ICUD10; +#endif + +#if SPC5_ICU_USE_EMIOS_CH17 && !defined(__DOXYGEN__) +extern ICUDriver ICUD11; +#endif + +#if SPC5_ICU_USE_EMIOS_CH18 && !defined(__DOXYGEN__) +extern ICUDriver ICUD12; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c new file mode 100644 index 000000000..ea07281a9 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c @@ -0,0 +1,951 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/pwm_lld.c + * @brief SPC5xx low level pwm driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the unified channel EMIOS_CH9 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH9 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the unified channel EMIOS_CH10 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH10 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the unified channel EMIOS_CH11 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH11 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the unified channel EMIOS_CH12 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH12 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the unified channel EMIOS_CH13 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH13 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD6 driver identifier. + * @note The driver PWMD6 allocates the unified channel EMIOS_CH14 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH14 || defined(__DOXYGEN__) +PWMDriver PWMD6; +#endif + +/** + * @brief PWMD7 driver identifier. + * @note The driver PWMD7 allocates the unified channel EMIOS_CH15 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH15 || defined(__DOXYGEN__) +PWMDriver PWMD7; +#endif + +/** + * @brief PWMD8 driver identifier. + * @note The driver PWMD8 allocates the unified channel EMIOS_CH23 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH23 || defined(__DOXYGEN__) +PWMDriver PWMD8; +#endif + +/** + * @brief PWMD9 driver identifier. + * @note The driver PWMD9 allocates the unified channel EMIOS_CH19 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH19 || defined(__DOXYGEN__) +PWMDriver PWMD9; +#endif + +/** + * @brief PWMD10 driver identifier. + * @note The driver PWMD10 allocates the unified channel EMIOS_CH20 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH20 || defined(__DOXYGEN__) +PWMDriver PWMD10; +#endif + +/** + * @brief PWMD11 driver identifier. + * @note The driver PWMD11 allocates the unified channel EMIOS_CH21 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH21 || defined(__DOXYGEN__) +PWMDriver PWMD11; +#endif + +/** + * @brief PWMD12 driver identifier. + * @note The driver PWMD12 allocates the unified channel EMIOS_CH22 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH22 || defined(__DOXYGEN__) +PWMDriver PWMD12; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief PWM IRQ handler. + * + * @param[in] pwmp pointer to the @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + + uint32_t sr = pwmp->emiosp->CH[pwmp->ch_number].CSR.R; + + if(sr && EMIOSS_OVFL){ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVFLC; + } + if(sr && EMIOSS_OVR){ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVRC; + } + if (sr && EMIOSS_FLAG){ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_FLAGC; + + if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) { + if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \ + pwmp->config->callback != NULL) { + pwmp->config->callback(pwmp); + } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \ + pwmp->config->channels[0].callback != NULL) { + pwmp->config->channels[0].callback(pwmp); + } + } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) { + if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \ + pwmp->config->callback != NULL) { + pwmp->config->callback(pwmp); + } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \ + pwmp->config->channels[0].callback != NULL) { + pwmp->config->channels[0].callback(pwmp); + } + } + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS_CH9 +#if !defined(SPC5_EMIOS_FLAG_F9_HANDLER) +#error "SPC5_EMIOS_FLAG_F9_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 +#if !defined(SPC5_EMIOS_FLAG_F10_HANDLER) +#error "SPC5_EMIOS_FLAG_F10_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 10 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F10_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 +#if !defined(SPC5_EMIOS_FLAG_F11_HANDLER) +#error "SPC5_EMIOS_FLAG_F11_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 11 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 +#if !defined(SPC5_EMIOS_FLAG_F12_HANDLER) +#error "SPC5_EMIOS_FLAG_F12_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 12 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F12_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 +#if !defined(SPC5_EMIOS_FLAG_F13_HANDLER) +#error "SPC5_EMIOS_FLAG_F13_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 13 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F13_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 +#if !defined(SPC5_EMIOS_FLAG_F14_HANDLER) +#error "SPC5_EMIOS_FLAG_F14_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 14 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F14_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 +#if !defined(SPC5_EMIOS_FLAG_F15_HANDLER) +#error "SPC5_EMIOS_FLAG_F15_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 15 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH19 +#if !defined(SPC5_EMIOS_FLAG_F19_HANDLER) +#error "SPC5_EMIOS_FLAG_F19_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 19 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F19_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 +#if !defined(SPC5_EMIOS_FLAG_F20_HANDLER) +#error "SPC5_EMIOS_FLAG_F20_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 20 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F20_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD10); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 +#if !defined(SPC5_EMIOS_FLAG_F21_HANDLER) +#error "SPC5_EMIOS_FLAG_F21_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 21 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F21_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 +#if !defined(SPC5_EMIOS_FLAG_F22_HANDLER) +#error "SPC5_EMIOS_FLAG_F22_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 22 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F22_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + +#if SPC5_PWM_USE_EMIOS_CH23 +#if !defined(SPC5_EMIOS_FLAG_F23_HANDLER) +#error "SPC5_EMIOS_FLAG_F23_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 23 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F23_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + /* eMIOSx channels initially all not in use.*/ + reset_emios_active_channels(); + +#if SPC5_PWM_USE_EMIOS_CH9 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.emiosp = &EMIOS; + PWMD1.ch_number = 9U; +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.emiosp = &EMIOS; + PWMD2.ch_number = 10U; +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.emiosp = &EMIOS; + PWMD3.ch_number = 11U; +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.emiosp = &EMIOS; + PWMD4.ch_number = 12U; +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.emiosp = &EMIOS; + PWMD5.ch_number = 13U; +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + /* Driver initialization.*/ + pwmObjectInit(&PWMD6); + PWMD6.emiosp = &EMIOS; + PWMD6.ch_number = 14U; +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + /* Driver initialization.*/ + pwmObjectInit(&PWMD7); + PWMD7.emiosp = &EMIOS; + PWMD7.ch_number = 15U; +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + /* Driver initialization.*/ + pwmObjectInit(&PWMD8); + PWMD8.emiosp = &EMIOS; + PWMD8.ch_number = 23U; +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + /* Driver initialization.*/ + pwmObjectInit(&PWMD9); + PWMD9.emiosp = &EMIOS; + PWMD9.ch_number = 19U; +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + /* Driver initialization.*/ + pwmObjectInit(&PWMD10); + PWMD10.emiosp = &EMIOS; + PWMD10.ch_number = 20U; +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + /* Driver initialization.*/ + pwmObjectInit(&PWMD11); + PWMD11.emiosp = &EMIOS; + PWMD11.ch_number = 21U; +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + /* Driver initialization.*/ + pwmObjectInit(&PWMD12); + PWMD12.emiosp = &EMIOS; + PWMD12.ch_number = 22U; +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + +#if SPC5_PWM_USE_EMIOS + +#if SPC5_EMIOS_NUM_CHANNELS == 16 + INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY; +#endif + +#if SPC5_EMIOS_NUM_CHANNELS == 24 + INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F19_NUMBER].R = SPC5_EMIOS_FLAG_F19_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F20_NUMBER].R = SPC5_EMIOS_FLAG_F20_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F21_NUMBER].R = SPC5_EMIOS_FLAG_F21_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F22_NUMBER].R = SPC5_EMIOS_FLAG_F22_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY; +#endif + +#endif + +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + uint32_t psc = 0; + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "pwm_lld_start(), #1", "too many channels"); + + if (pwmp->state == PWM_STOP) { +#if SPC5_PWM_USE_EMIOS_CH9 + if (&PWMD1 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + if (&PWMD2 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + if (&PWMD3 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + if (&PWMD4 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + if (&PWMD5 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + if (&PWMD6 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + if (&PWMD7 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + if (&PWMD8 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + if (&PWMD9 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + if (&PWMD10 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + if (&PWMD11 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + if (&PWMD12 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + + /* Set eMIOS Clock.*/ +#if SPC5_PWM_USE_EMIOS + active_emios_clock(NULL, pwmp); +#endif + + } + /* Configures the peripheral.*/ + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set clock prescaler and control register.*/ + psc = (SPC5_EMIOS_CLK / pwmp->config->frequency); + chDbgAssert((psc <= 0xFFFF) && + (((psc) * pwmp->config->frequency) == SPC5_EMIOS_CLK) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "pwm_lld_start(), #1", "invalid frequency"); + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 0; + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 1U; + pwmp->emiosp->CH[pwmp->ch_number].CCNTR.R = 1U; + pwmp->emiosp->CH[pwmp->ch_number].CADR.R = 0U; + pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = pwmp->config->period; + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= + EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | EMIOS_CCR_MODE_OPWFMB | 2U; + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_UCPREN;; + + /* Set output polarity.*/ + if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_EDPOL; + } else if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.R &= ~EMIOSC_EDPOL; + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number); + + } else if (pwmp->config->mode == PWM_ALIGN_CENTER){ + /* Not implemented.*/ + } + +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "pwm_lld_stop(), #1", "too many channels"); + + if (pwmp->state == PWM_READY) { + + /* Disables the peripheral.*/ +#if SPC5_PWM_USE_EMIOS_CH9 + if (&PWMD1 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + if (&PWMD2 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + if (&PWMD3 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + if (&PWMD4 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + if (&PWMD5 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + if (&PWMD6 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + if (&PWMD7 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + if (&PWMD8 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + if (&PWMD9 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + if (&PWMD10 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + if (&PWMD11 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + if (&PWMD12 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + + /* eMIOS clock deactivation.*/ +#if SPC5_PWM_USE_EMIOS + deactive_emios_clock(); +#endif + + } +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + + pwmp->period = period; + pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = period; + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + (void)channel; + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set pwm width.*/ + pwmp->emiosp->CH[pwmp->ch_number].CADR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL || \ + pwmp->config->channels[0].callback != NULL) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 1U; + } + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number); + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + (void)channel; + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 0; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number); + +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h new file mode 100644 index 000000000..c344a2006 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h @@ -0,0 +1,457 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/pwm_lld.h + * @brief SPC5xx low level pwm driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 1 + +/** + * @brief Edge-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_EDGE 0x00 + +/** + * @brief Center-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_CENTER 0x01 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH9) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH9 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH10) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH10 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH11) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH11 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH12) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH12 FALSE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH13) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH13 FALSE +#endif + +/** + * @brief PWMD6 driver enable switch. + * @details If set to @p TRUE the support for PWMD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH14) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH14 FALSE +#endif + +/** + * @brief PWMD7 driver enable switch. + * @details If set to @p TRUE the support for PWMD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH15) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH15 FALSE +#endif + +/** + * @brief PWMD8 driver enable switch. + * @details If set to @p TRUE the support for PWMD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH23) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH23 FALSE +#endif + +/** + * @brief PWMD9 driver enable switch. + * @details If set to @p TRUE the support for PWMD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH19) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH19 FALSE +#endif + +/** + * @brief PWMD10 driver enable switch. + * @details If set to @p TRUE the support for PWMD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH20) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH20 FALSE +#endif + +/** + * @brief PWMD11 driver enable switch. + * @details If set to @p TRUE the support for PWMD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH21) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH21 FALSE +#endif + +/** + * @brief PWMD12 driver enable switch. + * @details If set to @p TRUE the support for PWMD12 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH22) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH22 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F9_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F9_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F10_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F10_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F11_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F11_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F12_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F12_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F13_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F13_PRIORITY 7 +#endif + +/** + * @brief PWMD6 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F14_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F14_PRIORITY 7 +#endif + +/** + * @brief PWMD7 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F15_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F15_PRIORITY 7 +#endif + +/** + * @brief PWMD8 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F23_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F23_PRIORITY 7 +#endif + +/** + * @brief PWMD9 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F19_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F19_PRIORITY 7 +#endif + +/** + * @brief PWMD10 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F20_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F20_PRIORITY 7 +#endif + +/** + * @brief PWMD11 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F21_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F21_PRIORITY 7 +#endif + +/** + * @brief PWMD12 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F22_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F22_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS +#error "EMIOS not present in the selected device" +#endif + +#define SPC5_PWM_USE_EMIOS (SPC5_PWM_USE_EMIOS_CH9 || \ + SPC5_PWM_USE_EMIOS_CH10 || \ + SPC5_PWM_USE_EMIOS_CH11 || \ + SPC5_PWM_USE_EMIOS_CH12 || \ + SPC5_PWM_USE_EMIOS_CH13 || \ + SPC5_PWM_USE_EMIOS_CH14 || \ + SPC5_PWM_USE_EMIOS_CH15 || \ + SPC5_PWM_USE_EMIOS_CH19 || \ + SPC5_PWM_USE_EMIOS_CH20 || \ + SPC5_PWM_USE_EMIOS_CH21 || \ + SPC5_PWM_USE_EMIOS_CH22 || \ + SPC5_PWM_USE_EMIOS_CH23) + +#if !SPC5_PWM_USE_EMIOS +#error "PWM driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief PWM functional mode. + */ + pwmmode_t mode; +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief eMIOSx channel number. + */ + uint8_t ch_number; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS_CH9 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if SPC5_PWM_USE_EMIOS_CH10 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if SPC5_PWM_USE_EMIOS_CH11 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if SPC5_PWM_USE_EMIOS_CH12 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if SPC5_PWM_USE_EMIOS_CH13 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if SPC5_PWM_USE_EMIOS_CH14 && !defined(__DOXYGEN__) +extern PWMDriver PWMD6; +#endif + +#if SPC5_PWM_USE_EMIOS_CH15 && !defined(__DOXYGEN__) +extern PWMDriver PWMD7; +#endif + +#if SPC5_PWM_USE_EMIOS_CH23 && !defined(__DOXYGEN__) +extern PWMDriver PWMD8; +#endif + +#if SPC5_PWM_USE_EMIOS_CH19 && !defined(__DOXYGEN__) +extern PWMDriver PWMD9; +#endif + +#if SPC5_PWM_USE_EMIOS_CH20 && !defined(__DOXYGEN__) +extern PWMDriver PWMD10; +#endif + +#if SPC5_PWM_USE_EMIOS_CH21 && !defined(__DOXYGEN__) +extern PWMDriver PWMD11; +#endif + +#if SPC5_PWM_USE_EMIOS_CH22 && !defined(__DOXYGEN__) +extern PWMDriver PWMD12; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c new file mode 100644 index 000000000..0533b50e3 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c @@ -0,0 +1,117 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/spc5_emios.c + * @brief eMIOS200 helper driver code. + * + * @addtogroup SPC5xx_eMIOS200 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Number of active eMIOSx Channels. + */ +static uint32_t emios_active_channels; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +void reset_emios_active_channels() { + emios_active_channels = 0; +} + +uint32_t get_emios_active_channels() { + return emios_active_channels; +} + +void increase_emios_active_channels() { + emios_active_channels++; +} + +void decrease_emios_active_channels() { + emios_active_channels--; +} + +void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If this is the first Channel activated then the eMIOS0 is enabled.*/ + if (emios_active_channels == 1) { + SPC5_EMIOS_ENABLE_CLOCK(); + + /* Disable all unified channels.*/ + if (icup != NULL) { + icup->emiosp->MCR.B.GPREN = 0; + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER); + icup->emiosp->MCR.R |= EMIOSMCR_GPREN; + + icup->emiosp->MCR.B.GTBE = 1U; + + icup->emiosp->UCDIS.R = 0xFFFFFFFF; + + } else if (pwmp != NULL) { + pwmp->emiosp->MCR.B.GPREN = 0; + pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER); + pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN; + + pwmp->emiosp->MCR.B.GTBE = 1U; + + pwmp->emiosp->UCDIS.R = 0xFFFFFFFF; + + } + + } +} + +void deactive_emios_clock() { + /* If it is the last active channels then the eMIOS0 is disabled.*/ + if (emios_active_channels == 0) { + SPC5_EMIOS_DISABLE_CLOCK(); + + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +#endif /* HAL_USE_ICU || HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h new file mode 100644 index 000000000..2a93f1184 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h @@ -0,0 +1,114 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/spc5_emios.h + * @brief eMIOS200 helper driver header. + * + * @addtogroup SPC5xx_eMIOS200 + * @{ + */ + +#ifndef _SPC5_EMIOS_H_ +#define _SPC5_EMIOS_H_ + +#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EMIOSMCR_MDIS (1 << 30) +#define EMIOSMCR_FRZ (1 << 29) +#define EMIOSMCR_GTBE (1 << 28) +#define EMIOSMCR_GPREN (1 << 26) +#define EMIOSMCR_GPRE(n) ((n) << 8) + +#define EMIOSC_FREN (1 << 31) +#define EMIOSC_UCPRE(n) ((n) << 26) +#define EMIOSC_UCPREN (1 << 25) +#define EMIOSC_DMA (1 << 24) +#define EMIOSC_IF(n) ((n) << 19) +#define EMIOSC_FCK (1 << 18) +#define EMIOSC_FEN (1 << 17) +#define EMIOSC_FORCMA (1 << 13) +#define EMIOSC_FORCMB (1 << 12) +#define EMIOSC_BSL(n) ((n) << 9) +#define EMIOSC_EDSEL (1 << 8) +#define EMIOSC_EDPOL (1 << 7) +#define EMIOSC_MODE(n) ((n) << 0) + +#define EMIOS_BSL_COUNTER_BUS_A 0 +#define EMIOS_BSL_COUNTER_BUS_2 1 +#define EMIOS_BSL_INTERNAL_COUNTER 3 + +#define EMIOS_CCR_MODE_GPIO_IN 0 +#define EMIOS_CCR_MODE_GPIO_OUT 1 +#define EMIOS_CCR_MODE_SAIC 2 +#define EMIOS_CCR_MODE_SAOC 3 +#define EMIOS_CCR_MODE_IPWM 4 +#define EMIOS_CCR_MODE_IPM 5 +#define EMIOS_CCR_MODE_DAOC_B_MATCH 6 +#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7 +#define EMIOS_CCR_MODE_MC_CMS 16 +#define EMIOS_CCR_MODE_MC_CME 17 +#define EMIOS_CCR_MODE_MC_UP_DOWN 18 +#define EMIOS_CCR_MODE_OPWMT 38 +#define EMIOS_CCR_MODE_MCB 84 +#define EMIOS_CCR_MODE_OPWFMB 88 +#define EMIOS_CCR_MODE_OPWMCB_TE 92 +#define EMIOS_CCR_MODE_OPWMCB_LE 93 +#define EMIOS_CCR_MODE_OPWMB 96 + +#define EMIOSS_OVR (1 << 31) +#define EMIOSS_OVRC (1 << 31) +#define EMIOSS_OVFL (1 << 15) +#define EMIOSS_OVFLC (1 << 15) +#define EMIOSS_FLAG (1 << 0) +#define EMIOSS_FLAGC (1 << 0) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +void reset_emios_active_channels(void); +uint32_t get_emios_active_channels(void);; +void increase_emios_active_channels(void); +void decrease_emios_active_channels(void); +void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp); +void deactive_emios_clock(void); + +#endif /* HAL_USE_ICU || HAL_USE_PWM */ + +#endif /* _SPC5_EMIOS_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ICU-PWM/.cproject b/testhal/SPC563Mxx/ICU-PWM/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC563Mxx/ICU-PWM/.project b/testhal/SPC563Mxx/ICU-PWM/.project new file mode 100644 index 000000000..31139adbb --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/.project @@ -0,0 +1,38 @@ + + + SPC563Mxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC563M + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC563Mxx/ICU-PWM/Makefile b/testhal/SPC563Mxx/ICU-PWM/Makefile new file mode 100644 index 000000000..911a39668 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC563M64.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC563Mxx/ICU-PWM/chconf.h b/testhal/SPC563Mxx/ICU-PWM/chconf.h new file mode 100644 index 000000000..b4c46c7f6 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/chconf.h @@ -0,0 +1,536 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES FALSE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ICU-PWM/halconf.h b/testhal/SPC563Mxx/ICU-PWM/halconf.h new file mode 100644 index 000000000..24462dafd --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ICU-PWM/main.c b/testhal/SPC563Mxx/ICU-PWM/main.c new file mode 100644 index 000000000..60c451373 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/main.c @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT11, P11_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT11, P11_LED1); +} + +static PWMConfig pwmcfg = { + 80000, /* 80kHz PWM clock frequency.*/ + 20000, /* Initial PWM period 0.25s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; +icucnt_t last_width2, last_period2; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT11, P11_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT11, P11_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 80000, /* 80kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 8 and ICU driver 1. + * PIN80 is the PWM output. + * PIN63 is the ICU input. + * The two pins have to be externally connected together. + */ + + /* Sets PIN63 alternative function.*/ + SIU.PCR[179].R = 0b0000010100001100; + + /* Sets PIN80 alternative function.*/ + SIU.PCR[202].R = 0b0000011000001100; + + icuStart(&ICUD1, &icucfg); + icuEnable(&ICUD1); + pwmStart(&PWMD8, &pwmcfg); + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD8, 25000); + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables PWM channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD8, 0); + pwmStop(&PWMD8); + + /* + * Disables and stops the ICU drivers. + */ + + icuDisable(&ICUD1); + icuStop(&ICUD1); + + palClearPad(PORT11, P11_LED3); + palClearPad(PORT11, P11_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC563Mxx/ICU-PWM/mcuconf.h b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h new file mode 100644 index 000000000..be3ee85cf --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h @@ -0,0 +1,100 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC563Mxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 80 +#define SPC5_CLK_RFD SPC5_RFD_DIV4 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_PRIO 12 +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB FALSE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * ICU - PWM driver system settings. + */ +#define SPC5_ICU_USE_EMIOS_CH0 TRUE +#define SPC5_ICU_USE_EMIOS_CH1 TRUE +#define SPC5_ICU_USE_EMIOS_CH2 TRUE +#define SPC5_ICU_USE_EMIOS_CH3 TRUE +#define SPC5_ICU_USE_EMIOS_CH4 TRUE +#define SPC5_ICU_USE_EMIOS_CH5 TRUE +#define SPC5_ICU_USE_EMIOS_CH6 TRUE +#define SPC5_ICU_USE_EMIOS_CH8 TRUE + +#define SPC5_PWM_USE_EMIOS_CH9 TRUE +#define SPC5_PWM_USE_EMIOS_CH10 TRUE +#define SPC5_PWM_USE_EMIOS_CH11 TRUE +#define SPC5_PWM_USE_EMIOS_CH12 TRUE +#define SPC5_PWM_USE_EMIOS_CH13 TRUE +#define SPC5_PWM_USE_EMIOS_CH14 TRUE +#define SPC5_PWM_USE_EMIOS_CH15 TRUE +#define SPC5_PWM_USE_EMIOS_CH23 TRUE + +#define SPC5_EMIOS_GLOBAL_PRESCALER 200 diff --git a/testhal/SPC563Mxx/ICU-PWM/readme.txt b/testhal/SPC563Mxx/ICU-PWM/readme.txt new file mode 100644 index 000000000..f56bcf55b --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC563Mxx ICU and PWM drivers. + +** Board Setup ** + +Connect PIN63 and PIN80 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC564Axx/ICU_PWM/Makefile b/testhal/SPC564Axx/ICU_PWM/Makefile new file mode 100644 index 000000000..bdd72d6ac --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/Makefile @@ -0,0 +1,121 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc564axx_1.0.0.201305101230/component/lib/rsc/rules.mk diff --git a/testhal/SPC564Axx/ICU_PWM/chconf.h b/testhal/SPC564Axx/ICU_PWM/chconf.h new file mode 100644 index 000000000..b4c46c7f6 --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/chconf.h @@ -0,0 +1,536 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES FALSE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/ICU_PWM/halconf.h b/testhal/SPC564Axx/ICU_PWM/halconf.h new file mode 100644 index 000000000..24462dafd --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/ICU_PWM/main.c b/testhal/SPC564Axx/ICU_PWM/main.c new file mode 100644 index 000000000..e571bbeed --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/main.c @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT11, P11_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT11, P11_LED1); +} + +static PWMConfig pwmcfg = { + 80000, /* 80kHz PWM clock frequency.*/ + 20000, /* Initial PWM period 0.25s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; +icucnt_t last_width2, last_period2; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT11, P11_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT11, P11_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 80000, /* 80kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 6 and ICU driver 3. + * PIN78 is the PWM output. + * PIN65 is the ICU input. + * The two pins have to be externally connected together. + */ + + /* Sets PIN65 alternative function.*/ + SIU.PCR[181].R = 0b0000010100001100; + + /* Sets PIN78 alternative function.*/ + SIU.PCR[193].R = 0b0000011000001100; + + icuStart(&ICUD3, &icucfg); + icuEnable(&ICUD3); + pwmStart(&PWMD6, &pwmcfg); + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD6, 25000); + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables PWM channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD6, 0); + pwmStop(&PWMD6); + + /* + * Disables and stops the ICU drivers. + */ + + icuDisable(&ICUD3); + icuStop(&ICUD3); + + palClearPad(PORT11, P11_LED3); + palClearPad(PORT11, P11_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC564Axx/ICU_PWM/mcuconf.h b/testhal/SPC564Axx/ICU_PWM/mcuconf.h new file mode 100644 index 000000000..a2e46cd16 --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/mcuconf.h @@ -0,0 +1,108 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC564Axx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC564Axx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 75 +#define SPC5_CLK_RFD SPC5_RFD_DIV2 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_PRIO 12 +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB FALSE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * ICU - PWM driver system settings. + */ +#define SPC5_ICU_USE_EMIOS_CH0 TRUE +#define SPC5_ICU_USE_EMIOS_CH1 TRUE +#define SPC5_ICU_USE_EMIOS_CH2 TRUE +#define SPC5_ICU_USE_EMIOS_CH3 TRUE +#define SPC5_ICU_USE_EMIOS_CH4 TRUE +#define SPC5_ICU_USE_EMIOS_CH5 TRUE +#define SPC5_ICU_USE_EMIOS_CH6 TRUE +#define SPC5_ICU_USE_EMIOS_CH7 TRUE +#define SPC5_ICU_USE_EMIOS_CH8 TRUE +#define SPC5_ICU_USE_EMIOS_CH16 TRUE +#define SPC5_ICU_USE_EMIOS_CH17 TRUE +#define SPC5_ICU_USE_EMIOS_CH18 TRUE + +#define SPC5_PWM_USE_EMIOS_CH9 TRUE +#define SPC5_PWM_USE_EMIOS_CH10 TRUE +#define SPC5_PWM_USE_EMIOS_CH11 TRUE +#define SPC5_PWM_USE_EMIOS_CH12 TRUE +#define SPC5_PWM_USE_EMIOS_CH13 TRUE +#define SPC5_PWM_USE_EMIOS_CH14 TRUE +#define SPC5_PWM_USE_EMIOS_CH15 TRUE +#define SPC5_PWM_USE_EMIOS_CH19 TRUE +#define SPC5_PWM_USE_EMIOS_CH20 TRUE +#define SPC5_PWM_USE_EMIOS_CH21 TRUE +#define SPC5_PWM_USE_EMIOS_CH22 TRUE +#define SPC5_PWM_USE_EMIOS_CH23 TRUE + +#define SPC5_EMIOS_GLOBAL_PRESCALER 200 diff --git a/testhal/SPC564Axx/ICU_PWM/readme.txt b/testhal/SPC564Axx/ICU_PWM/readme.txt new file mode 100644 index 000000000..f6018c4f3 --- /dev/null +++ b/testhal/SPC564Axx/ICU_PWM/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC564Axx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC564Axx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC564Axx ICU and PWM drivers. + +** Board Setup ** + +Connect PIN65 and PIN78 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com