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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5128 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-02-07 14:11:22 +00:00
parent d078530805
commit 46ccb5a5f2
3 changed files with 11 additions and 30 deletions
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6
os/hal/platforms/SPC560Pxx/hal_lld.h
View File

@ -256,7 +256,7 @@
/** /**
* @brief FMPLL1 IDF divider value. * @brief FMPLL1 IDF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_IDF_VALUE 5 #define SPC5_FMPLL1_IDF_VALUE 5
@ -264,7 +264,7 @@
/** /**
* @brief FMPLL1 NDIV divider value. * @brief FMPLL1 NDIV divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_NDIV_VALUE 60 #define SPC5_FMPLL1_NDIV_VALUE 60
@ -272,7 +272,7 @@
/** /**
* @brief FMPLL1 ODF divider value. * @brief FMPLL1 ODF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 #define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4

1
os/hal/platforms/SPC56ELxx/hal_lld.c
View File

@ -130,7 +130,6 @@ void spc_clock_init(void) {
/* Run modes initialization.*/ /* Run modes initialization.*/
ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
// ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */

34
os/hal/platforms/SPC56ELxx/hal_lld.h
View File

@ -150,7 +150,6 @@
* @{ * @{
*/ */
#define SPC5_ME_ME_RESET (1U << 0) #define SPC5_ME_ME_RESET (1U << 0)
#define SPC5_ME_ME_TEST (1U << 1)
#define SPC5_ME_ME_SAFE (1U << 2) #define SPC5_ME_ME_SAFE (1U << 2)
#define SPC5_ME_ME_DRUN (1U << 3) #define SPC5_ME_ME_DRUN (1U << 3)
#define SPC5_ME_ME_RUN0 (1U << 4) #define SPC5_ME_ME_RUN0 (1U << 4)
@ -204,7 +203,6 @@
* @name ME_RUN_PCx registers bits definitions * @name ME_RUN_PCx registers bits definitions
* @{ * @{
*/ */
#define SPC5_ME_RUN_PC_TEST (1U << 1)
#define SPC5_ME_RUN_PC_SAFE (1U << 2) #define SPC5_ME_RUN_PC_SAFE (1U << 2)
#define SPC5_ME_RUN_PC_DRUN (1U << 3) #define SPC5_ME_RUN_PC_DRUN (1U << 3)
#define SPC5_ME_RUN_PC_RUN0 (1U << 4) #define SPC5_ME_RUN_PC_RUN0 (1U << 4)
@ -259,7 +257,7 @@
/** /**
* @brief FMPLL0 IDF divider value. * @brief FMPLL0 IDF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_IDF_VALUE 5 #define SPC5_FMPLL0_IDF_VALUE 5
@ -267,15 +265,15 @@
/** /**
* @brief FMPLL0 NDIV divider value. * @brief FMPLL0 NDIV divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_NDIV_VALUE 32 #define SPC5_FMPLL0_NDIV_VALUE 60
#endif #endif
/** /**
* @brief FMPLL0 ODF divider value. * @brief FMPLL0 ODF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 #define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
@ -290,7 +288,7 @@
/** /**
* @brief FMPLL1 IDF divider value. * @brief FMPLL1 IDF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_IDF_VALUE 5 #define SPC5_FMPLL1_IDF_VALUE 5
@ -298,7 +296,7 @@
/** /**
* @brief FMPLL1 NDIV divider value. * @brief FMPLL1 NDIV divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_NDIV_VALUE 60 #define SPC5_FMPLL1_NDIV_VALUE 60
@ -306,7 +304,7 @@
/** /**
* @brief FMPLL1 ODF divider value. * @brief FMPLL1 ODF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/ */
#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 #define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
@ -325,20 +323,6 @@
SPC5_ME_ME_STOP0) SPC5_ME_ME_STOP0)
#endif #endif
/**
* @brief TEST mode settings.
*/
#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/** /**
* @brief SAFE mode settings. * @brief SAFE mode settings.
*/ */
@ -459,8 +443,7 @@
* mode. * mode.
*/ */
#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) #if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ #define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_DRUN | \ SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \ SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \ SPC5_ME_RUN_PC_RUN1 | \
@ -750,7 +733,6 @@
/*===========================================================================*/ /*===========================================================================*/
typedef enum { typedef enum {
SPC5_RUNMODE_TEST = 1,
SPC5_RUNMODE_SAFE = 2, SPC5_RUNMODE_SAFE = 2,
SPC5_RUNMODE_DRUN = 3, SPC5_RUNMODE_DRUN = 3,
SPC5_RUNMODE_RUN0 = 4, SPC5_RUNMODE_RUN0 = 4,