Enabled USB on G4.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13054 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/halconf.h

@@ -184,7 +184,7 @@
  * @brief   Enables the USB subsystem.
  */
 #if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
-#define HAL_USE_USB                         FALSE
+#define HAL_USE_USB                         TRUE
 #endif
 
 /**

demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h

@@ -270,6 +270,10 @@
 /*
  * USB driver system settings.
  */
+#define STM32_USB_USE_USB1                  TRUE
+#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
+#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
+#define STM32_USB_USB1_LP_IRQ_PRIORITY      14
 
 /*
  * WDG driver system settings.

os/hal/ports/STM32/STM32G4xx/hal_lld.h

@@ -270,7 +270,8 @@
 
 #define STM32_FDCANSEL_MASK     (3U << 24U) /**< FDCANSEL mask.             */
 #define STM32_FDCANSEL_HSE      (0U << 24U) /**< FDCAN source is HSE.       */
-#define STM32_FDCANSEL_PLLQCLK  (2U << 24U) /**< FDCAN source is PLLQCLK.   */
+#define STM32_FDCANSEL_PLLQCLK  (1U << 24U) /**< FDCAN source is PLLQCLK.   */
+#define STM32_FDCANSEL_PCLK1    (2U << 24U) /**< FDCAN source is PCLK1.    */
 
 #define STM32_CLK48SEL_MASK     (3U << 26U) /**< CLK48SEL mask.             */
 #define STM32_CLK48SEL_HSI48    (0U << 26U) /**< CLK48 source is HSI48.     */
@@ -1693,6 +1694,35 @@
   #error "invalid source selected for SAI1 clock"
 #endif
 
+/**
+ * @brief   FDCAN clock frequency.
+ */
+#if (STM32_FDCANSEL == STM32_FDCANSEL_HSE) || defined(__DOXYGEN__)
+  #define STM32_FDCANCLK            STM32_HSECLK
+
+#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
+  #define STM32_FDCANCLK            STM32_PLL_Q_CLKOUT
+
+#elif STM32_FDCANSEL == STM32_FDCANSEL_PCLK1
+  #define STM32_FDCANCLK            STM32_PCLK1
+
+#else
+  #error "invalid source selected for FDCAN clock"
+#endif
+
+/**
+ * @brief   48MHz clock frequency.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
+  #define STM32_48CLK               STM32_HSI48CLK
+
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK
+  #define STM32_48CLK               STM32_PLL_Q_CLKOUT
+
+#else
+  #error "invalid source selected for 48MHz clock"
+#endif
+
 /**
  * @brief   ADC clock frequency.
  */
@@ -1753,6 +1783,11 @@
  */
 #define STM32_TIMCLK2               STM32_TIMP2CLK
 
+/**
+ * @brief   USB clock point.
+ */
+#define STM32_USBCLK                STM32_48CLK
+
 /**
  * @brief   Flash settings.
  */

os/hal/ports/STM32/STM32G4xx/platform.mk

@@ -36,6 +36,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
 
 # Shared variables

os/hal/ports/STM32/STM32G4xx/stm32_isr.h

@@ -227,6 +227,14 @@
 #define STM32_UART4_NUMBER                  52
 #define STM32_UART5_NUMBER                  53
 #define STM32_LPUART1_NUMBER                91
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER               Vector8C
+#define STM32_USB1_LP_HANDLER               Vector90
+#define STM32_USB1_HP_NUMBER                19
+#define STM32_USB1_LP_NUMBER                20
 /** @} */
 
 /*===========================================================================*/

tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl

@@ -281,6 +281,10 @@
 /*
  * USB driver system settings.
  */
+#define STM32_USB_USE_USB1                  ${doc.STM32_USB_USE_USB1!"FALSE"}
+#define STM32_USB_LOW_POWER_ON_SUSPEND      ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
+#define STM32_USB_USB1_HP_IRQ_PRIORITY      ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
+#define STM32_USB_USB1_LP_IRQ_PRIORITY      ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
 
 /*
  * WDG driver system settings.