From 473a0c858afe5e27571ffa1bb0ee1b162c7aa13d Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Mon, 31 Jul 2023 09:15:59 +0000
Subject: [PATCH] STM32C0 drivers test-compiled. RTC requires rework because it
 has no TAMP.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16354 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h | 2 +-
 os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h         | 4 ++--
 os/hal/ports/STM32/STM32C0xx/stm32_isr.h           | 2 ++
 os/hal/ports/STM32/STM32C0xx/stm32_rcc.h           | 2 +-
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h b/demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h
index 101f52ecb..77e46b881 100644
--- a/demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h
@@ -73,7 +73,7 @@
 #define STM32_I2C1SEL                       STM32_I2C1SEL_PCLK
 #define STM32_I2S1SEL                       STM32_I2S1SEL_SYSCLK
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
-#define STM32_RTCSEL                        STM32_RTCSEL_NOCLOCK
+#define STM32_RTCSEL                        STM32_RTCSEL_LSE
 
 /*
  * Shared IRQ settings.
diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
index ab5305739..34cba507e 100644
--- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
@@ -209,8 +209,8 @@
 /*===========================================================================*/
 
 /* Supported devices checks.*/
-#if !defined(STM32G0XX) && !defined(STM32WLXX)
-#error "ADCv5 only supports G0 and WL STM32 devices"
+#if !defined(STM32C0XX) && !defined(STM32G0XX) && !defined(STM32WLXX)
+#error "ADCv5 only supports C0, G0 and WL STM32 devices"
 #endif
 
 /* Registry checks.*/
diff --git a/os/hal/ports/STM32/STM32C0xx/stm32_isr.h b/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
index f6b017a5d..1739955ab 100644
--- a/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
@@ -61,6 +61,8 @@
 
 #define STM32_DMA1_CH1_NUMBER               9
 #define STM32_DMA1_CH23_NUMBER              10
+#define STM32_DMA1_CH2_NUMBER               STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER               STM32_DMA1_CH23_NUMBER
 
 #define STM32_DMA1_CH1_CMASK                0x00000001U
 #define STM32_DMA1_CH2_CMASK                0x00000006U
diff --git a/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
index 0e151503b..c67d97c1b 100644
--- a/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
@@ -494,7 +494,7 @@
  *
  * @api
  */
-#define rccEnableTIM16(lp) rccEnableAPB(RCC_APBENR2_TIM16EN, lp)
+#define rccEnableTIM16(lp) rccEnableAPBR2(RCC_APBENR2_TIM16EN, lp)
 
 /**
  * @brief   Disables the TIM16 peripheral clock.